MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 224

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Each comparator control register features a TAG bit, which controls whether the comparator match causes a state sequencer
transition immediately or tags the opcode at the matched address. If a comparator is enabled for tagged comparisons, the
address stored in the comparator match address registers must be an opcode address.
Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state
sequencer state occurs. If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can
a breakpoint be generated. Using End alignment, when the tagged instruction is about to be executed and the next transition is
to Final State then a breakpoint is generated immediately, before the tagged instruction is carried out.
R/W monitoring, access size (SZ) monitoring and data bus monitoring are not useful if tagging is selected, since the tag is
attached to the opcode at the matched address and is not dependent on the data bus nor on the type of access. Thus these bits
are ignored if tagging is selected.
When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
Tagging is disabled when the BDM becomes active.
4.32.4.7
It is possible to generate breakpoints from channel transitions to final state or using software to write to the TRIG bit in the DBGC1
register.
4.32.4.7.1
Breakpoints can be generated when the state sequencer transitions to the Final State. If configured for tagging, then the
breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue.
If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if
Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see
no tracing session is selected, breakpoints are requested immediately.
If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing trigger alignment.
4.32.4.7.2
If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is defined by the TALIGN bit. If a tracing
session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin
aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see
tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible with a single write to DBGC1,
setting ARM and TRIG simultaneously.
4.32.4.7.3
If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an effect. When the
associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent comparator
channel match, it has no effect, since tracing has already started.
If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is activated by the BGND and
the breakpoint to SWI is suppressed.
4.32.4.7.3.1
Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU is executing out of
BDM firmware, thus comparator matches and associated breakpoints are disabled. In addition, while executing a BDM TRACE
command, tagging into BDM is disabled. If BDM is not active, the breakpoint gives priority to BDM requests over SWI requests
Freescale Semiconductor
BRK
0
0
0
0
1
1
Breakpoints
Breakpoints From Comparator Channels
Breakpoints Generated Via The TRIG Bit
Breakpoint Priorities
DBG Breakpoint Priorities And BDM Interfacing
TALIGN
0
0
1
1
x
x
Table 330. Breakpoint Setup For CPU Breakpoints
DBGBRK
0
1
0
1
1
0
MM912_634 Advance Information, Rev. 4.0
Start Trace Buffer at trigger. A breakpoint request occurs when Trace Buffer is full
Terminate tracing and generate breakpoint immediately on trigger
Fill Trace Buffer until trigger, then breakpoint request occurs
Fill Trace Buffer until trigger then disarm (no breakpoints)
Start Trace Buffer at trigger (no breakpoints)
Terminate tracing immediately on trigger
Breakpoint Alignment
Table
330). If no
Table
330). If
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