MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 314

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.40.4.5
This section provides details of all available Flash commands launched by a command write sequence. The ACCERR bit in the
FSTAT register will be set during the command write sequence if any of the following illegal steps are performed, causing the
command not to be processed by the Memory Controller:
If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation will return invalid data.
If the SFDIF or DFDIF flags were not previously set when the invalid read operation occurred, both the SFDIF and DFDIF flags
will be set.
If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting any command write
sequence (see
4.40.4.5.1
The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased.
Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash
memory space is erased. The CCIF flag will set after the Erase Verify All Blocks operation has completed.
4.40.4.5.2
The Erase Verify Block command allows the user to verify that an entire P-Flash or D-Flash block has been erased. The FCCOB
upper global address bits determine which block must be verified.
Freescale Semiconductor
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Starting any command write sequence that programs or erases Flash memory before initializing the FCLKDIV register
Writing an invalid command as part of the command write sequence
For additional possible errors, refer to the error handling table provided for each command
Register
FSTAT
Note:
215.
216.
217.
Mass Erase
Program Flash
Section
Flash Command Description
A ‘Margin Read’ is any read after executing the margin setting commands ‘Set User Margin Level’ or ‘Set Field
See the Note on margin settings in
The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’.
Margin Level’ with anything but the ‘normal’ level specified.
A Flash word or phrase must be in the erased state before being programmed. Cumulative
programming of bits within a Flash word or phrase is not allowed.
Erase Verify All Blocks Command
Erase Verify Block Command
(215)
4.40.3.2.7).
CCOBIX[2:0]
MGSTAT1
MGSTAT0
Table 449. Erase Verify All Blocks Command FCCOB Requirements
ACCERR
Error Bit
FPVIOL
Table 448. Allowed P-Flash and D-Flash Simultaneous Operations
000
Table 450. Erase Verify All Blocks Command Error Handling
Read
Set if CCOBIX[2:0] != 000 at command launch
None
Set if any errors have been encountered during the read
Set if any non-correctable errors have been encountered during the read
MM912_634 Advance Information, Rev. 4.0
Margin Read
Section 4.40.4.5.12
0x01
CAUTION
(215)
FCCOB Parameters
and
Data Flash
Program
Section
Error Condition
4.40.4.5.13.
Not required
Sector Erase
Mass Erase
OK
(217)
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