MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 333

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.41.3.7
This read-only register contains information about the ongoing D2D interface transaction. The register content will be updated
when a new transaction starts. In error cases the user can track back, which transaction failed.
Freescale Semiconductor
D2DBSY
ADR[7:0]
Reset
Reset
D2DIF
NBLK
Field
Field
RWB
Offset 0x3
W
11:8
SZ8
R
Offset 0x4/0x5
W
R
5:0
7:0
15
14
13
12
7
6
RWB
D2D Interrupt Flag — This read-only flag reflects the status of the D2DINT Pin. The D2D interrupt flag can only be cleared by a
target specific interrupt acknowledge sequence.
D2D Initiator Busy — This read-only status bit indicates that a D2D transaction is ongoing.
Reserved, should be masked to ensure compatibility with future versions of this interface.
Transaction Read-Write Direction — This read-only bit reflects the direction of the transaction
Transaction Size — This read-only bit reflects the data size of the transaction
Reserved, should be masked to ensure compatibility with future versions of this interface.
Transaction Mode — This read-only bit reflects the mode of the transaction
Reserved, should be masked to ensure compatibility with future versions of this interface.
Transaction Address — Those read-only bits contain the address of the transaction
15
0
D2DIF
0
1
0
1
0
1
0
1
0
1
D2DI Address Buffer Register (D2DADR)
7
0
SZ8
External Interrupt is negated
External Interrupt is asserted
D2D initiator idle.
D2D initiator transaction ongoing.
14
Write Transaction
Read Transaction
16-bit transaction.
8-bit transaction.
Blocking transaction.
Non-blocking transaction.
0
13
D2DBSY
0
0
6
0
NBLK
Table 497. D2DI Address Buffer Register Bit Descriptions
12
0
Table 496. D2DI Address Buffer Register (D2DADR)
Table 495. D2DSTAT1 Register Field Descriptions
Table 494. D2DI Status Register 1 (D2DSTAT1)
11
0
0
MM912_634 Advance Information, Rev. 4.0
5
0
0
10
0
0
9
0
0
4
0
0
Description
Description
8
0
0
7
0
3
0
0
6
0
5
0
2
0
0
4
0
ADR[7:0]
3
0
1
0
0
2
0
Access: User read
Access: User read
1
0
0
0
0
0
0
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