MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 56

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The Lx Control register for the not available Lx input must be written 0.
A not available Lx input can not be selected as Wake-up Source and must have its LxWE bit set to 0.
The Wake-up Source Register for not available Lx inputs must be ignored.
The Conversion Control Register for the not available Lx analog input (3…8) must always be written 0.
The Conversion Complete Register for the not available Lx analog input (3.8) must be ignored.
The ADC Data Result Register for the not available Lx analog input (3.8) must be ignored.
4.3.3.2.3
For the not available Lx inputs, the following functions are limited:
Freescale Semiconductor
0x8C-0
Offset
0x08
0x09
0x12
0x14
0x82
0x83
0x84
0x85
x97
•
•
•
No Wake-up feature / Cyclic Sense
No Digital Input
No Analog Input and conversion via ADC
ADC Data Result Register x
ADC Data Result Register x
Wake Up Control Register
Wake Up Source Register
ADC Conversion Ctrl Reg
ADC Conversion Ctrl Reg
ADC Conv Complete Reg
ADC Conv Complete Reg
Lx Control Register
Lx Status Register
ACCSR (hi)
ACCSR (lo)
Functional Considerations
ACCR (hi)
ACCR (lo)
ADRx (hi)
ADRx (lo)
Name
LXCR
WCR
WSR
LXR
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
adrx 1
adrx 9
CH15
CC15
MM912_634 Advance Information, Rev. 4.0
FWU
CH7
CC7
7
0
0
CSSEL
LINWU
adrx 8
adrx 0
CH14
CC14
CH6
CC6
6
0
0
L5WU
adrx 7
L5WE
L5DS
CH5
CC5
L5
5
0
0
0
L4WU
adrx 6
L4WE
L4DS
CH12
CC12
CH4
CC4
L4
4
0
L3WU
adrx 5
L3WE
L3DS
CH11
CC11
CH3
CC3
L3
3
0
L2WU
adrx 4
L2WE
L2DS
CH10
CC10
CH2
CC2
L2
2
0
L1WE
L1WU
adrx 3
L1DS
CH9
CH1
CC9
CC1
L1
1
0
L0WE
L0WU
adrx 2
L0DS
CH8
CH0
CC8
CC0
L0
0
0
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