MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 251

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When a non-zero value is loaded from Flash to CR[2:0] the COP timeout period is started.
A change of the COPOSCSEL bit (writing a different value or loosing UPOSC status) re-starts the COP timeout period.
In Normal Mode the COP timeout period is restarted if either of these conditions is true:
In Special Mode, any write access to CPMUCOP register restarts the COP timeout period.
4.38.3.2.10
Freescale Semiconductor
WRTMASK
RSBCK
CR[2:0]
WCOP
1.
2.
3.
Field
2–0
7
6
5
Writing a non-zero value to CR[2:0] (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0.
Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0.
Changing RSBCK bit from “0” to “1”.
Window COP Mode Bit — When set, a write to the CPMUARMCOP register must occur in the last 25% of the selected period.
A write during the first 75% of the selected period generates a COP reset. As long as all writes occur during this window, $55
can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts and the user must wait until
the next window before writing to CPMUARMCOP.
rates.
COP and RTI Stop in Active BDM Mode Bit
Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits while writing
the CPMUCOP register. It is intended for BDM writing the RSBCK without changing the content of WCOP and CR[2:0].
COP Watchdog Timer Rate Select — These bits select the COP timeout rate (see
CR[2:0] enables the COP counter and starts the timeout period. A COP counter timeout causes a System Reset. This can be
avoided by periodically (before timeout) initializing the COP counter via the CPMUARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at highest timeout
period (
Reserved Register CPMUTEST0
This reserved register is designed for factory test purposes only, and is not intended for
general user access. Writing to this register when in Special Mode can alter the S12CPMU’s
functionality.
0
1
0
1
0
1
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in Special Mode
2
Normal COP operation
Window COP operation
Allows the COP and RTI to keep running in Active BDM mode.
Stops the COP and RTI counters whenever the part is in Active BDM mode.
Write of WCOP and CR[2:0] has an effect with this write of CPMUCOP
Write of WCOP and CR[2:0] has no effect with this write of CPMUCOP. (Does not count for “write once”.)
24 cycles) in normal COP mode (Window COP mode disabled):
CR2
0
0
0
0
1
1
1
1
CR1
0
0
1
1
0
0
1
1
Table 357. CPMUCOP Field Descriptions
MM912_634 Advance Information, Rev. 4.0
Table 358. COP Watchdog Rates
CR0
0
1
0
1
0
1
0
1
NOTE
Table 358
(COPCLK is either IRCCLK or OSCCLK
depending on the COPOSCSEL bit)
Description
COPCLK - Cycles to Timeout
shows the duration of this window for the seven available COP
COP disabled
2
2
2
2
2
2
2
14
16
18
20
22
23
24
Table
358). Writing a nonzero value to
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