MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 139

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.20.5.2
To eliminate the Analog Digital Converter Offset, an automatic compensation is implemented. The compensation is based on a
calibrated voltage reference connected to ADC Channel 15. The reference trim is accomplished by the correct CTRx Register
content. See
To activate the Offset compensation feature, the OCE bit in the ADC Config Register (ACR) has to be set, and the CH15 has to
be enabled when starting a new conversion, by writing to the ADC Conversion Control Register (ACCR). The compensation will
work with single and sequence conversion.
4.20.5.3
The conversion timing is based on the ADCCLK generated by the ADC prescaler (PS) out of the D2DCLK signal. The prescaler
needs to be configured to have the ADCCLK match the specified f
Freescale Semiconductor
Section 4.26, “MM912_634 - Analog Die
Automatic Offset Compensation
Conversion Timing
Note:
133.
Channel
10
12
13
14
15
11
7
8
9
Internal “bg1p25sleep” reference.
AD7 - L4 Analog Input
AD8 - L5 Analog Input
Current Sense
Voltage Sense
Temperature Sense
not implemented
Bandgap
Calibration Reference
VS1 Sense
(133)
Figure 36. Automatic Offset Compensation
ACCR – ADC Conversion Control Register
MM912_634 Advance Information, Rev. 4.0
OCE – Offset Compensation Enable = 1
Table 209. Analog Channels
MCU – IFR (4C..4F) => CTR0..3
Offset is calculated as
Adjust CHx Result by
Read ADRx after SCF is set
difference between
result and 8 LSB
calculated offset
Sample CH15
Sample CHx
Trimming. The reference is factory trimmed to 8 LSB.
CH15=1 + CHx = 1
Description
ADC
clock limits.
CH15 is a trimmed
reference of 8 LSB
(requires CTRx)
VS1SENSE
BANDGAP
VSENSE
TSENSE
ISENSE
AD7
AD8
CAL
n.i.
139