MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 180

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.30.5
4.30.5.1
After system reset, software should:
4.30.5.2
The interrupt request scheme makes it possible to nest I bit maskable interrupt requests handled by the CPU. I bit maskable
interrupt requests can be interrupted by an interrupt request with a higher priority.
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per default. In order to make an
interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I bit in the CCR (CLI). After clearing the I bit, other
I bit maskable interrupt requests can interrupt the current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
4.30.5.3
4.30.5.3.1
Every I bit maskable interrupt request is capable of waking the MCU from stop mode. To determine whether an I bit maskable
interrupts is qualified to wake-up the CPU or not, the same conditions as in normal run mode are applied during stop mode: If the
I bit in the CCR is set, all I bit maskable interrupts are masked from waking-up the MCU.
Since there are no clocks running in stop mode, only interrupts which can be asserted asynchronously can wake-up the MCU
from stop mode.
The X bit maskable interrupt request can wake up the MCU from stop mode at anytime, even if the X bit in CCR is set.
If the X bit maskable interrupt request is used to wake-up the MCU with the X bit in the CCR set, the associated ISR is not called.
The CPU then resumes program execution with the instruction following the WAI or STOP instruction. This features works the
same rules like any interrupt request, i.e. care must be taken that the X interrupt request used for wake-up remains active at least
until the system begins execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur.
Freescale Semiconductor
Note:
161.
162.
163.
(Vector base + 0x00F0–0x0082)
1.
2.
3.
1.
2.
3.
4.
(Vector base + 0x00F4)
(Vector base + 0x00F2)
(Vector base + 0x0080)
16 bits vector address based
D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt
D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt
Vector Address
Initialize the interrupt vector base register if the interrupt vector table is not located at the default location
(0xFF80–0xFFF9).
Enable I bit maskable interrupts by clearing the I bit in the CCR.
Enable the X bit maskable interrupt by clearing the X bit in the CCR.
Service interrupt, e.g., clear interrupt flags, copy data, etc.
Clear I bit in the CCR by executing the instruction CLI (thus allowing other I bit maskable interrupt requests)
Process data
Return from interrupt by executing the instruction RTI
Initialization/Application Information
Initialization
Interrupt Nesting
Wake-up from Stop Mode
CPU Wake-up from Stop Mode
(161)
X bit maskable interrupt request (XIRQ or D2D error interrupt)
IRQ or D2D interrupt request
Device specific I bit maskable interrupt sources (priority determined by the low byte of the vector address,
in descending order)
Spurious interrupt
Table 258. Exception Vector Map and Priority
MM912_634 Advance Information, Rev. 4.0
(163)
Source
(162)
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