MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 187

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses 0x3_FF00 to 0x3_FFFF.
BDM registers are mapped to addresses 0x3_FF00 to 0x3_FF0B. The BDM uses these registers which are readable anytime by
the BDM. However, these registers are not readable by user programs.
When BDM is activated while CPU executes code overlapping with BDM firmware space the saved program counter (PC) will be
auto incremented by one from the BDM firmware, no matter what caused the entry into BDM active mode (BGND instruction,
BACKGROUND command or breakpoints). In such a case the PC must be set to the next valid address via a WRITE_PC
command before executing the GO command.
4.31.4.3
Hardware commands are used to read and write target system memory locations and to enter active background debug mode.
Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, Flash, I/O and control registers.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for
execution, although, they can still be executed in this mode. When executing a hardware command, the BDM sub-block waits for
a free bus cycle so that the background access does not disturb the running application program. If a free cycle is not found within
128 clock cycles, the CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the
operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However, if an operation
requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle.
The BDM hardware commands are listed in
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations are not normally in the
system memory map but share addresses with the application in memory. To distinguish between physical memory locations that
share the same address, BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle. This allows
the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application memory map.
Freescale Semiconductor
Note:
168.
WRITE_BD_WORD
READ_BD_WORD
WRITE_BD_BYTE
READ_BD_BYTE
BACKGROUND
WRITE_WORD
ACK_DISABLE
ACK_ENABLE
READ_WORD
WRITE_BYTE
READ_BYTE
Command
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete
for all BDM WRITE commands.
BDM Hardware Commands
If an attempt is made to activate BDM before being enabled, the CPU resumes normal
instruction execution after a brief delay. If BDM is not enabled, any hardware
BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed.
Opcode
(hex)
EC
CC
D5
D6
E4
E0
E8
C4
C0
C8
90
16-bit data out
16-bit data out
16-bit data out
16-bit data out
16-bit address
16-bit address
16-bit address
16-bit address
16-bit address
16-bit address
16-bit address
16-bit address
16-bit data in
16-bit data in
16-bit data in
16-bit data in
None
None
None
Data
Table
MM912_634 Advance Information, Rev. 4.0
Table 266. Hardware Commands
Enter background mode if BDM is enabled. If enabled, an ACK will be issued when the
part enters active background mode.
Enable Handshake. Issues an ACK pulse after the command is executed.
Disable Handshake. This command does not issue an ACK pulse.
Read from memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
Read from memory with standard BDM firmware lookup table in map.
Must be aligned access.
Read from memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
Read from memory with standard BDM firmware lookup table out of map. Must be
aligned access.
Write to memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
Write to memory with standard BDM firmware lookup table in map.
Must be aligned access.
Write to memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
Write to memory with standard BDM firmware lookup table out of map.
Must be aligned access.
266.
NOTE
Description
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