MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 30

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The maximum D-Flash programming time is given by:
3.6.2.1.1.16
Typical D-Flash sector erase times, expected on a new device where no margin verify fails occur, is given by:
Maximum D-Flash sector erase times is given by:
The D-Flash sector erase time is ~5.0 ms on a new device and can extend to ~20 ms as the flash is cycled.
3.6.2.1.2
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors, and burn-in to
screen early life failures.
The data retention and program/erase cycling failure rates are specified at the operating conditions noted. The program/erase
cycle count on the sector is incremented every time a sector or mass erase event is executed.
Freescale Semiconductor
Note:
C
D Erase all blocks (mass erase) time
D Erase verify all blocks (blank check) time
D Unsecure Flash time
D P-Flash block erase time
D P-Flash erase verify (blank check) time
D P-Flash sector erase time
D P-Flash phrase programming time
D D-Flash sector erase time
D D-Flash erase verify (blank check) time
D D-Flash one word programming time
D D-Flash two word programming time
D D-Flash three word programming time
D D-Flash four word programming time
D D-Flash four word programming time crossing row boundary
37.
38.
39.
40.
41.
Bus frequency
Operating frequency
Typical program and erase times are based on typical f
Maximum program and erase times are based on minimum f
t
The maximum device bus clock is specified as fBUS.
Typical value for a new device.
t
t
CYC
dera
dera
= 1 / f


t
5025
20100
dpgm
NVMBUS
(40)
Erase D-Flash Sector (FCMD=0x12)
NVM Reliability Parameters
All values shown in


---------------- -
f



NVMOP
---------------- -
f

NVMOP
14
1
1
+

+
54 N
+
Rating
700
3400


W
------------------- -
f
Table 40
NVMBUS

Table 39. NVM Timing Characteristics (FTMRC)

+
------------------- -
f
1
NVMBUS

14 BC
1
MM912_634 Advance Information, Rev. 4.0

are preliminary and subject to further characterization.
 

---------------- -
f
NVMOP
NVMOP
1
NOTE
NVMOP
and maximum f


+


and maximum f

Symbol
f
t
t
t
500
f
NVMBUS
t
t
PCHECK
DCHECK
t
t
t
t
DPGM4C
NVMOP
t
CHECK
PMASS
t
t
DPGM1
DPGM2
DPGM3
DPGM4
t
PPGM
t
PERA
DERA
mass
UNS
+

NVMBUS
750

NVMBUS
N
.
Min
0.8
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1

+
.

100 BC

Typ
5
100
100
100
226
100
170
241
328
311
1.0
20
—
—
—
—
(41)
(37)

Electrical Characteristics


------------------- -
f
NVMBUS
1
Max
19200
17200
2800
1.05
130
130
130
285
107
185
262
339
357
32
26
26
(38)


Unit
MHz
MHz
t
t
t
CYC
CYC
CYC
ms
ms
ms
ms
ms
s
s
s
s
s
s
(39)
30