MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 287

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the
parallel SPI data register after the last bit is shifted in.
After 2n
Figure 108
diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly
between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the
master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI.
Note:
Freescale Semiconductor
199.
•
•
End of Idle State
n depends on the selected transfer width, refer to
(199)
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
CHANGE O
SEL SS (O)
Master only
SEL SS (I)
MSB first (LSBFE = 0):
t
t
t
t
MOSI pin
MISO pin
Data that was previously in the master SPI data register should now be in the slave data register and the data that was
in the slave data register should be in the master.
The SPIF flag in the SPI status register is set, indicating that the transfer is complete.
LSB first (LSBFE = 1):
L
T
I
L
, t
= Minimum idling time between transfers (minimum SS high time)
= Minimum leading time before the first SCK edge
= Minimum trailing time after the last SCK edge
is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The
T
, and t
(last) SCK edges:
Figure 108. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width Selected (XFRW = 0)
I
are guaranteed for the master mode and required for the slave mode.
t
L
MSB
LSB
1
2
Begin
Bit 6
Bit 1
3
MM912_634 Advance Information, Rev. 4.0
4
Bit 5
Bit 2
Section 4.39.3.2.2, “SPI Control Register 2 (SPICR2)
5
6
Bit 4
Bit 3
7
Transfer
8
Bit 3
Bit 4
9
10
Bit 2
Bit 5
11
12
Bit 1
Bit 6
13 14
End
MSB
15
LSB
16
Minimum 1/2 SCK
t
T
for t
Begin of Idle State
T
t
, t
I
l
, t
L
t
L
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