MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 132

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Setting a force output compare bit, FOCn, causes an output compare on channel n. A forced output compare does not set the
channel flag.
A successful output compare on channel 3 overrides output compares on all other output compare channels. The output compare
3 mask register masks the bits in the output compare 3 data register. The timer counter reset enable bit, TCRE, enables channel
3 output compares to reset the timer counter. A channel 3 output compare can reset the timer counter even if the IOC3 pin is
being used as the pulse accumulator input.
Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch.
When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.
4.19.5
4.19.5.1
The reset state of each individual bit is listed within the Register Description section
details the registers and their bit-fields.
4.19.6
4.19.6.1
This section describes interrupts originated by the TIM16B4C block.
communicate with the MCU.
4.19.6.2
The TIM16B4C uses a total of 5 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent. More
information on interrupt vector offsets and interrupt numbers can be found in the
4.19.6.2.1
These active high outputs are asserted by the module to request a timer channel 3–0 interrupt, following an input capture or
output compare event on these channels [3-0]. For the interrupt to be asserted on a specific channel, the enable, CnI bit of TIE
register should be set. These interrupts are serviced by the system controller.
4.19.6.2.2
This active high output will be asserted by the module to request a timer overflow interrupt, following the timer counter overflow
when the overflow enable bit (TOI) bit of TFLG2 register is set. This interrupt is serviced by the system controller.
Freescale Semiconductor
Interrupt
C[3:0]F
TOF
Resets
Interrupts
General
General
Description of Interrupt Operation
Channel [3:0] Interrupt
Timer Overflow Interrupt (TOF)
Offset
-
-
Vector
-
-
Priority
MM912_634 Advance Information, Rev. 4.0
Table 196. TIM16B4C Interrupts
-
-
Timer Channel 3-0
Timer Overflow
Source
Table 196
lists the interrupts generated by the TIM16B4C to
Section 4.7, “Interrupts
4.19.3, “Memory Map and
Active high timer channel interrupts 3-0
Timer Overflow interrupt
Description
Registers“, which
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