MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 278

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.39.3.2.2
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Freescale Semiconductor
Note:
191.
Reset
MODFEN
BIDIROE
W
R
XFRW
SPC0
Field
6
4
3
1
0
n is used later in this document as a placeholder for the selected transfer width.
-
Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL becomes
the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and SPIDRL form a 16-bit data
register. Please refer to
and the interrupt flag clearing mechanism. In master mode, a change of this bit will abort a transmission in progress and force
the SPI system into idle state.
Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is
cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value
of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin configuration, refer to
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer of the SPI,
when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output buffer of the MOSI port, in
slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a
transmission in progress and force the SPI into idle state.
Reserved — For internal use
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in
of this bit will abort a transmission in progress and force the SPI system into idle state.
7
0
0
SPI Control Register 2 (SPICR2)
0 8-bit Transfer Width (n = 8)
1 16-bit Transfer Width (n = 16)
0
1
0
1
MODFEN
SS port pin is not used by the SPI.
SS port pin with MODF feature.
Output buffer disabled.
Output buffer enabled.
0
0
1
1
XFRW
6
0
Section 4.39.3.2.4, “SPI Status Register (SPISR)
SSOE
0
1
0
1
= Unimplemented or Reserved
Table 391. SPI Control Register 2 (SPICR2)
Table 390. SS Input / Output Selection
Table 392. SPICR2 Field Descriptions
MM912_634 Advance Information, Rev. 4.0
(191)
5
0
0
(191)
SS input with MODF feature
SS is slave select output
MODFEN
SS not used by SPI
SS not used by SPI
4
0
Master Mode
Description
BIDIROE
3
0
for information about transmit/receive data handling
2
0
0
Table
Slave Mode
SS input
SS input
SS input
SS input
393. In master mode, a change
SPISWAI
1
0
Table
390. In master
SPC0
0
0
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