MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 196

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.31.4.10
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single
instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM is
active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed.
This facilitates stepping or tracing through the user code one instruction at a time.
If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is
executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt
service routine.
Be aware when tracing through the user code that the execution of the user code is done step by step but peripherals are free
running. Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer
exist.
Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will result in a return address
pointing to BDM firmware address space.
When tracing through user code which contains stop instructions the following will happen when the stop instruction is traced:
4.31.4.11
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more
than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting
for a rising edge on BKGD in order to answer the SYNC request pulse. If the rising edge is not detected, the target will keep
waiting forever without any timeout limit.
Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as a valid bit transmission,
and not as a SYNC request. The target will keep waiting for another falling edge marking the start of a new bit. If, however, a new
falling edge is not detected by the target within 512 clock cycles since the last falling edge, a timeout occurs and the current
command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset.
If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the
command to be disregarded. The data is not available for retrieval after the timeout has occurred. This is the expected behavior
if the handshake protocol is not enabled. In order to allow the data to be retrieved even with a large clock frequency mismatch
(between BDM and CPU) when the hardware handshake protocol is enabled, the time out between a read command and the
data retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data
from an issued read command. However, once the handshake pulse (ACK pulse) is issued, the timeout feature is re-activated,
meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512 serial clock
cycles time frame after the ACK pulse had been issued. After that period, the read command is discarded and the data is no
longer available for retrieval. Any negative edge in the BKGD pin after the timeout period is considered to be a new command or
a SYNC request.
Note that whenever a partially issued command, or partially retrieved data, has occurred the timeout in the serial communication
is active. This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges
and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received
command or data retrieved to be disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is
considered by the target as the start of a new BDM command, or the start of a SYNC request pulse.
Freescale Semiconductor
The CPU enters stop mode and the TRACE1 command can not be finished before leaving the low power mode. This is
the case because BDM active mode can not be entered after CPU executed the stop instruction. However all BDM
hardware commands except the BACKGROUND command are operational after tracing a stop instruction and still being
in stop mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is operational.
As soon as stop mode is exited the CPU enters BDM active mode and the saved PC value points to the entry of the
corresponding interrupt service routine.
In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command will be discarded
when tracing a stop instruction. Hence there is no ACK pulse when BDM active mode is entered as part of the TRACE1
command after CPU exited from stop mode. All valid commands sent during CPU being in stop mode or after CPU
exited from stop mode will have an ACK pulse. The handshake feature becomes disabled only when system stop mode
has been reached. Hence after a system stop mode the handshake feature must be enabled again by sending the
ACK_ENABLE command.
Instruction Tracing
Serial Communication Timeout
MM912_634 Advance Information, Rev. 4.0
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