MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 331

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The Clock Divider will provide the waveforms as shown in
cycle is shorter than 50% or equal but never longer, since this is beneficial for the transaction speed.
4.41.3.4
This register is used to enable the D2DI interrupt and set number of D2DCLK cycles before a timeout error is asserted.
Freescale Semiconductor
D2DCLKDIV
Reset
bus clock
D2DIE
Field
Offset 0x1
W
D2DCW
D2DEN
R
Field
7
4:2
1:0
7
6
5
-
00
01
10
11
D2D Interrupt Enable — Enables the external interrupt
D2DIE
D2DI Enable — Enables the D2DI module. This bit is write-once in normal mode and can always be written in special modes.
D2D Connection Width — Sets the number of data lines used by the interface. This bit is write-once in normal modes and
can always be written in special modes.
Reserved — For internal use
Reserved, should be written to 0 to ensure compatibility with future versions of this interface.
Interface Clock Divider — Determines the frequency of the interface clock. These bits are write-once in normal modes and
can be always written in special modes. See
0
1
D2DI Control Register 1 (D2DCTL1)
7
0
0
1
the IDLE command; the D2DCLK is driven by the divided bus clock.
0
1
00
01
10
11
External Interrupt is disabled
External Interrupt is enabled
D2DI initiator is disabled. No lines are not used, the pins have their GPIO (secondary) function.
D2DI initiator is enabled. After setting D2DEN=1 the D2DDAT[7:0] (or [3:0], see D2DCW) lines are driven low with
Lines D2DDAT[3:0] are used for four line data transfer. D2DDAT[7:4] are unused.
All eight interface lines D2DDAT[7:0] are used for data transfer.
Encoding 0. Bus clock divide by 1.
Encoding 1. Bus clock divide by 2.
Encoding 2. Bus clock divide by 3.
Encoding 3. Bus clock divide by 4.
Figure 118. Interface Clock Waveforms for various D2DCLKDIV Encoding
6
0
0
Table 489. D2DCTL0 Register Field Descriptions
Table 491. D2DCTL1 Register Field Descriptions
Table 490. D2DI Control Register 1 (D2DCTL1)
MM912_634 Advance Information, Rev. 4.0
5
0
0
Figure 118
Figure
4
0
0
Description
Description
118. The duty cycle of the clock is not always 50%, the high
for details on the clock waveforms
3
0
2
0
TIMOUT[3:0]
1
0
Access: User read/write
0
0
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