MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 286

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input
pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or
MSB of the SPI shift register, depending on the LSBFE bit.
If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd
numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift
register, depending on the LSBFE bit.
When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS
input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the nth
is considered complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF
flag in the SPI status register is set.
Note:
4.39.4.3
During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial
clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection
of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a
master SPI device, the slave select line can be used to indicate multiple-master bus contention.
4.39.4.3.1
Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity.
The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format.
The CPHA clock phase control bit selects one of two fundamentally different transmission formats.
Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the
phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having
different requirements.
4.39.4.3.2
The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first data bit of the master into
the slave. In some peripherals, the first bit of the slave’s data is available at the slave’s data out pin as soon as the slave is
selected. In this format, the first SCK edge is issued a half cycle after SS has become low.
A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched
from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit.
After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial
input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered
edges and shifted on even numbered edges.
Freescale Semiconductor
198.
n depends on the selected transfer width, refer to
Transmission Formats
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with
SPC0 set in slave mode will corrupt a transmission in progress and must be avoided.
Clock Phase and Polarity Controls
CPHA = 0 Transfer Format
SHIFT REGISTER
GENERATOR
BAUD RATE
MASTER SPI
Figure 107. Master/Slave Transfer Block Diagram
MM912_634 Advance Information, Rev. 4.0
MISO
MOSI
SCK
SS
Section 4.39.3.2.2, “SPI Control Register 2 (SPICR2)
V
NOTE
DD
MISO
MOSI
SCK
SS
SHIFT REGISTER
SLAVE SPI
(198)
shift, the transfer
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