MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 282

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Note:
Note:
192.
193.
194.
195.
196.
XFRW Bit
XFRW Bit
SPTEF
MODF
Field
SPIF
0
1
7
5
4
0
1
Data in SPIDRH is lost in this case.
SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read of SPIDRL after reading SPISR with
Any write to SPIDRH or SPIDRL with SPTEF = 0 is effectively ignored.
Data in SPIDRH is undefined in this case.
SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR
SPIF = 1.
with SPTEF = 1.
SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For information about
clearing SPIF Flag, please refer to
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For information about
clearing this bit and placing data into the transmit data register, please refer to
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault detection
is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Register 2
to the SPI control register 1.
0
1
0
1
0
1
Read SPISR with SPTEF = 1
Read SPISR with SPTEF = 1
Transfer not yet complete.
New data copied to SPIDR.
SPI data register not empty.
SPI data register empty.
Mode fault has not occurred.
Mode fault has occurred.
Read SPISR with SPIF = 1
Read SPISR with SPIF = 1
(SPICR2)”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write
Table 400. SPTEF Interrupt Flag Clearing Sequence
Table 399. SPIF Interrupt Flag Clearing Sequence
Table 398. SPISR Field Descriptions
MM912_634 Advance Information, Rev. 4.0
Table
SPTEF Interrupt Flag Clearing Sequence
.
SPIF Interrupt Flag Clearing Sequence
then
then
then
then
Byte Write to SPIDRH
Description
Byte Read SPIDRH
Word Write to (SPIDRH:SPIDRL)
Byte Write to SPIDRL
Word Read (SPIDRH:SPIDRL)
Write to SPIDRL
(194)(196)
Byte Read SPIDRL
Table
(193)
Read SPIDRL
.
or
or
Section 4.39.3.2.2, “SPI Control
or
or
Byte Write to SPIDRL
(194)
(194)(195)
(192)
Byte Read SPIDRL
(194)
(194)
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