MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 254

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Read: Anytime
Write: Only in special mode
4.38.3.2.13
This register is used to restart the COP timeout period.
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
4.38.3.2.14
The CPMULVCTL register allows the configuration of the low-voltage detect features.
Freescale Semiconductor
0x02F1
0x003E
0x003F
Reset
fm_cs[7:0]
W
W
Reset
R
R
Field
7
W
R
Writing any value other than $55 or $AA causes a COP reset. To restart the COP timeout period write $55 followed by
a write of $AA. These writes do not need to occur back to back, but the sequence ($55, $AA) must be completed prior
to COP end of timeout period to avoid a COP reset. Sequences of $55 writes are allowed. When the WCOP bit is set,
$55 and $AA writes must be done in the last 25% of the selected timeout period; writing any value in the first 75% of
the selected period will cause a COP reset.
Bit 7
Frequency Modulation Amplitude Bits— If fmcs_reg_sel = 1 (CPMUTEST0 register) then fm_cs[7:0] adds current of
0(fm_cs=$00) to 1 (fm_cs=$ff) times the value determined by FME1, FM0 bits to the VCO current. As a result VCOCLK
frequency will increase.
0
7
0
0
7
0
7
S12CPMU COP Timer Arm/Reset Register (CPMUARMCOP)
Low Voltage Control Register (CPMULVCTL)
Bit 6
= Unimplemented or Reserved
0
6
6
0
0
6
0
Table 365. Low Voltage Control Register (CPMULVCTL)
Table 364. S12CPMU CPMUARMCOP Register
Figure 87. Reserved Register (CPMUFMCS)
Table 363. CPMUFMCS Field Descriptions
Bit 5
MM912_634 Advance Information, Rev. 4.0
0
5
5
0
0
5
0
Bit 4
0
4
0
0
4
0
4
fm_cs[7:0]
Description
Bit 3
3
0
3
0
0
3
0
LVDS
Bit 2
0
2
2
0
0
2
LVIE
Bit 1
0
1
1
0
0
1
LVIF
Bit 0
0
0
0
0
0
0
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