MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 245

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
LOCKIF
UPOSC
OSCIF
PORF
LOCK
LVRF
Field
RTIF
ILAF
7
6
5
4
3
2
1
0
Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing
a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1. Writing
a 0 has no effect.
Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1.
Writing a 0 has no effect.
PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by writing a 1.
Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
Lock Status Bit — LOCK reflects the current state of PLL lock condition. Writes have no effect. While PLL is unlocked
(LOCK=0) fPLL is fVCO / 4 to protect the system from high core clock frequencies during the PLL stabilization time tlock.
Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to MMC chapter for details. This
flag can only be cleared by writing a 1. Writing a 0 has no effect.
Oscillator Interrupt Flag — OSCIF is set to 1 when UPOSC status bit changes. This flag can only be cleared by writing a 1.
Writing a 0 has no effect.If enabled (OSCIE=1), OSCIF causes an interrupt request.
Oscillator Status Bit — UPOSC reflects the status of the oscillator. Writes have no effect. While UPOSC=0 the OSCCLK
going to the MSCAN module is off. Entering Full Stop Mode UPOSC is cleared.
The Adaptive Oscillator Filter uses the VCO clock as a reference to continuously qualify the
external oscillator clock. Because of this, the PLL is always active and a valid PLL
configuration is required for the system to work properly. Furthermore, the Adaptive
Oscillator Filter is used to determine the status of the external oscillator (reflected in the
UPOSC bit). Since this function also relies on the VCO clock, loosing PLL lock status
(LOCK=0, except for entering Pseudo Stop mode) means loosing the oscillator status
information as well (UPOSC=0).
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RTI timeout has not yet occurred.
RTI timeout has occurred.
Power on reset has not occurred.
Power on reset has occurred.
Low voltage reset has not occurred.
Low voltage reset has occurred.
No change in LOCK bit.
LOCK bit has changed.
VCOCLK is not within the desired tolerance of the target frequency. f
VCOCLK is within the desired tolerance of the target frequency. f
Illegal address reset has not occurred.
Illegal address reset has occurred.
No change in UPOSC bit.
UPOSC bit has changed.
The oscillator is off or oscillation is not qualified by the PLL.
The oscillator is qualified by the PLL.
Table 344. CPMUFLG Field Descriptions
MM912_634 Advance Information, Rev. 4.0
NOTE
Description
PLL
PLL
= f
VCO
= f
VCO
/(POSTDIV+1).
/4.
245