TMPM382FSFG Toshiba, TMPM382FSFG Datasheet

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TMPM382FSFG

Manufacturer Part Number
TMPM382FSFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM382FSFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
64K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
64
Package
QFP(14x14)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
1
I2c/sio (ch)
1
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
10
16-bit Timer / Counter
6
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
32-bit TX System RISC
TMPM380FWDFG
TMPM380FYDFG
Semiconductor Company
TMPM380FWFG
TMPM382FWFG
TMPM380FYFG
TMPM382FSFG
TX03 Series

TMPM382FSFG Summary of contents

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... TX System RISC TX03 Series TMPM380FYDFG TMPM380FWDFG TMPM380FYFG TMPM380FWFG TMPM382FWFG TMPM382FSFG Semiconductor Company ...

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Date Revision 2011/3/17 Revision History Rev 1 First Release ...

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ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. **************************************************************************************************************** TMPM380/M380 - ...

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... Synchronous serial Port (SSP) (16) Remote control signal preprocesser (RMC) (17) 12-bit A/D converter (ADC) (18) Standby mode (19) Clock generator(CG) (20) Endian (21) Maximum operating frequency (22) Operating voltage range (23) Temperature range TMPM382FWFG TMPM382FSFG - Internal: 55 factors - External: 8 factors INT0/1/2/3/4/5/8/F 48 pins - Input/Output: 47 pins - Output: 1pin - 1 channel ch0 ...

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... On chip Flash ROM On chip RAM TMPM380FYFG TMPM380FYDFG ** TMPM380FWFG ** TMPM380FWDFG ** TMPM382FWFG ** TMPM382FSFG ** 1.1 Features (1) ARM Cortex-M3 microcontroller core 1) Improved code efficiency has been realized through the use of Thumb®-2 instruction - New 16-bit Thumb ...

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Over and Features (5) Power-on Reset Circuit (POR) (6) Voltage Detection Circuit (VLTD) (7) Oscillation Frequency Detector (OFD) (8) DMA contorller: 2 channels - Incr to Incr / Incr to No-Incr / No-Incr to Incr / No-Incr to No-Incr ...

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Serial bus interface (I2C/SIO): 2 channels - Either I2C bus mode or synchronous mode can be selected (15) Synchronous serial Port (SSP): 2 channels - SPI flame format /SSI flame format /Microwire flame format - 16byte FIFO equipped (16bit*8) ...

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Over and Features 1.2 Block Diagram I-Code Cortex-M3 CPU D-Code System Debug NVIC DMAC(2ch) UART/SIO(5ch) I2C/SIO(2ch) SSP(2ch) TMRB(8ch) RMC (1ch) MPT(3ch) ENC (2ch) I/F NANO FLASH I/F RAM I/F BOOT ROM Bus Bridge Int. High-speed oscillator CG PLL WDT ...

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I-Code Cortex-M3 CPU D-Code System Debug NVIC DMAC(2ch) Bus Bridge UART/SIO(3ch) I2C/SIO(1ch) SSP(1ch) TMRB(8ch) RMC (1ch) MPT(1ch) Fig1-1 TMPM382 block diagram TMPM380/M382 - 3.3V I/F NANO REGULATOR FLASH 1.5V I/F RAM I/F BOOT ROM Int. High-speed ...

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... Pin Layout and Pin Functions This chapter describes the pin layout, pin names and pin functions of TMPM380FYFG, TMPM380FWFG, TMPM380FYDFG,TMPM380FWDFG TMPM382FWFG and TMPM382FSFG. 2.1 Pin Layout (Top view) Fig.2-1 shows the pin layout of TMPM380FYFG and TMPM380FWFG. PD4/SCLK2/CTS2 PD3/INT9 PD2/ENCZ0/INTD PD1/ENCB0/TB5OUT PD0/ENCA0/TB5IN/INTC DVSS PC7/MT0IN/RXD4 ...

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Pin Layout and Pin Functions Fig.2-2 shows the pin layout of TMPM380FYDFG and TMPM380FWDFG. PD6/RXD2 PD5/TXD2 PD4/SCLK2/CTS2 PD3/INT9 PD2/ENCZ0/INTD PD1/ENCB0/TB5OUT PD0/ENCA0/TB5IN/INTC DVSS PC7/MT0IN/RXD4 PC6/EMG0/GEMG0 / TXD4 PC5/ZO0/MTOUT10/MTTB0IN/SCLK4/CTS4 PC4/WO0/MTOUT00/MTTB0OUT PC3/YO0/SP0FSS PC2/VO0/SP0CLK/SCK0 PC1/XO0/SP0DI/SCL0/SI0 PC0/UO0/SP0DO/SDA0/SO0 DVDD5 PP1/XT2 PP0/XT1 PM1/X2 DVSS PM0/X1 DVSS ...

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... Fig.2-3 shows the pin layout of TMPM382FWFG and TMPM382FSFG. DVSS PC7/MTIN/RXD4 PC6/EMG0/GEMG0 / TXD4 PC5/ZO0/MTOUT10/MTTB0IN/SCLK4/CTS4 PC4/WO0/MTOUT00/MTTB0OUT PC3/YO0/SP0FSS PC2/VO0/SP0CLK/SCK0 PC1/XO0/SP0DI/SCL0/SI0 PC0/UO0/SP0DO/SDA0/SO0 DVDD5 PP1/XT2 PP0/XT1 PM1/X2 DVSS PM0/X1 DVSS 1 TMPM382FWFG 5 TMPM382FSFG 64pin (14x14) 10 Top view 15 Fig. 2-3 Pin layout (TMPM382FxFG) TMPM380/M382 - TMPM380/M382 48 PI1/AIN9 PI0/AIN8 PH7/AIN7 ...

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Pin Layout and Pin Functions 2.2 Pin function Table 2-1 lists the pin functions of TMPM380FxFG/DFG. Table 2-4 shows the operating voltage of each pin, and Table 2-5 shows the voltage range of every pin. M380FxDFG M380FxFG QFP100 LQFP100 ...

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M380FxDFG M380FxFG Pin name QFP100 LQFP100 PC0 UO0 16 14 SP0DO SDA0 / SO0 17 15 DVDD5 PP1 18 16 XT2 PP0 19 17 XT1 PM1 DVSS PM0 DVSS PG0 ...

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Pin Layout and Pin Functions M380FxDFG M380FxFG QFP100 LQFP100 ...

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M380FxDFG M380FxFG Pin name QFP100 LQFP100 PN7 57 55 MT2IN INTE PL2 58 56 INTF 59 57 DVSS 60 58 MODE 61 59 RVDD5 62 60 RESET 63 61 VOUT3 PH0 64 62 AIN0 INT0 PH1 65 63 AIN1 INT1 ...

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Pin Layout and Pin Functions M380FxDFG M380FxFG QFP100 LQFP100 ...

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Table 2-2 lists the pin functions of TMPM382FxFG. Table 2-4 shows the operating voltage of each pin, and Table 2-5 shows the voltage range of every pin. Pin No. Pin name 1 DVSS PC7 2 MTIN RXD4 PC6 EMG0 3 ...

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Pin Layout and Pin Functions Pin No. PA0 17 TB0IN INT3 PA1 18 TB0OUT SCOUT PA2 19 TB1IN INT4 PA3 20 TB1OUT RXIN PA4 21 SCLK1 CTS1 PA5 22 TXD1 TB6OUT PA6 23 RXD1 TB6IN PA7 24 INT8 TB4IN ...

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Table 2-2 Pin functions (3/4) Pin No. Pin name Output during Reset PL2 33 INTF 34 DVSS 35 MODE 36 RVDD5 37 RESET 38 VOUT3 PH0 39 AIN0 INT0 PH1 40 AIN1 INT1 PH2 41 AIN2 INT2 PH3 42 AIN3 ...

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Pin Layout and Pin Functions Pin No. 49 AVSS 50 AVDD5 51 DVSS 52 DVDD5 PL0 53 BOOT 54 FTEST3 PB0 55 TRACECLK PB1 56 TRACEDATA0 PB2 57 TRACEDATA1 PB3 58 TMS SWDIO PB4 59 TCK SWCLK PB5 60 ...

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Table 2-4 Operating voltage of each Pin Pin name PM0,PM1 X1,X2 PP0,PP1 XT1,XT2 RESET MODE PA to PG,PL,PN I/O PH,PI,PJ AIN0 to AIN17 Table 2-5 voltage range of each pin Pin name RVDD5 DVDD5 AVDD5 VOUT3 DVSS AVSS Note : ...

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Processor Core 3.1 Processor Core The TX03 series has a high-performance 32-bit processor core (the ARM Cortex-M3 processor core). For information on the operations of this processor core, please refer to the “Cortex-M3 Technical Reference Manual” issued by ARM ...

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Processor Core 3.5 Exclusive access TMPM380/M382 does not support EXCLUSIVE ACCESS. 3.6 Reset operation 3.6.1 Initial state The internal circuits, register settings and pin status are undefined right after the power-on. The state continues until the applied. 3.6.2 Reset ...

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Dubug Interface 4.1 Specification Overview The TMPM380/M382 contains the Serial Wire JTAG Debug Port (SWJ-DP) unit for interfacing with the In-Circuit Emulator (ICE) and the Embedded Trace Macrocell output. Trace data is output to the dedicated pins (TRACEDATA[0]-[1], SWV) ...

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Dubug Interface The table 4-2 below summarizes the debug interface pin functions and related port settings after reset. Table 4-2 Debug interface pins and port setting after reset PORT Initial (Bit Setting name) PORT PB0 PORT PB1 PORT PB2 ...

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Peripherals operation during HALT mode (one time stop of running program) When Cortex-M3 CPU core going into HALT mode by break operation during debbug mode,Watch dog timer(WDT) count stops automatically. Other peripherals continue operation. (Note) 16-bit timer (TMRB) and ...

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Memory Map The memory maps for the TMPM380 are based on the ARM Cortex-M3 processor core memory map. The internal ROM, internal RAM and internal I/O of the TMPM380 are mapped to the code, SRAM and peripheral regions of ...

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Memory Map 5.1 TMPM380FY Memory Map Fig 5-1 shows the memory map of the TMPM380FY. Single chip mode 0xFFFF FFFF Vendor Specific 0xE010 0000 0xE00F FFFF CPU Register Region 0xE000 0000 0x41FF FFFF 0x4000 0000 0x2000 3FFF Internal RAM ...

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TMPM380FW/382FW Memory Map Fig 5-2 shows the memory map of the TMPM380FW/382FW. Single chip mode 0xFFFF FFFF Vendor Specific 0xE010 0000 0xE00F FFFF CPU Register Region 0xE000 0000 0x41FF FFFF Internal IO 0x4000 0000 0x2000 2FFF Internal RAM (12K) ...

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Memory Map 5.3 TMPM382FS Memory Map Fig 5-3 shows the memory map of the TMPM382FS. Single chip mode 0xFFFF FFFF Vendor Specific 0xE010 0000 0xE00F FFFF CPU Register Region 0xE000 0000 0x41FF FFFF 0x4000 0000 0x2000 1FFF Internal RAM ...

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Clock/Mode Control 6.1 Features The clock/mode control block enables to select clock gear, prescaler clock and warm-up of the PLL (including clock multiplication circuit) and oscillator. The low power consumption mode can reduce power consumption.by mode transitions. This chapter ...

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Clock/Mode Control 6.2 Registers 6.2.1 Register List Table 6-1 shows registers and addresses of the clock generator. System control register Oscillation control register Standby control register PLL selection register System clock selection register Table 6-1 Registers of Clock Generator ...

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Detailed Description of Registers 6.2.2.1 System Control Register (CGSYSCR: 7 Bit symbol - Read/Write After reset 0 Function 15 Bit symbol - Read/Write After reset 0 Function “0” is read. 23 Bit symbol - Read/Write R/W After reset 0 ...

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Clock/Mode Control 6.2.2.2 Oscillation Control Register (CGOSCCR: 0x4004_0204) 7 Bit symbol - Read/Write R/W After reset 0 Function 15 Bit symbol WUODR1 Read/Write R/W After reset 0 Function Bit1:0 for warm-up counter value. If high-speed oscillator is selected,<Bit15:14><WO UDR ...

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Specifies Port M or X1/X2. When external oscillator is used, set PMCR/PMPUP /PMPDN/PMIE of Port M to disable. After reset, PMCR/PMPUP/PMPDN/PMIE are set to disable. <Bit 19><WUPSEL2> : Select source clock for warm-up timer between internal oscillator(OSC1) ...

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Clock/Mode Control 6.2.2.3 Standby Control Register (CGSTBYCR: 0x4004_0208) 7 Bit symbol - Read/Write After reset 0 Function 15 Bit symbol - Read/Write After reset 0 Function 23 Bit symbol - Read/Write After reset 0 Function 31 Bit symbol - ...

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PLL Selection Register (CGPLLSEL: 0x4004_020C) 7 Bit symbol - Read/Write After reset 0 Function 15 Bit symbol - Read/Write After reset 0 Function 23 - Bit symbol Read/Write 0 After reset Function 31 - Bit symbol Read/Write 0 After ...

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Clock/Mode Control 6.2.2.5 System Clock Selection Register (CGCKSEL: 0x4004_0210) 7 Bit symbol - Read/Write After reset 0 Function 15 Bit symbol - Read/Write After reset 0 Function 23 Bit symbol - Read/Write After reset 0 Function 31 Bit symbol ...

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Clock Control 6.3.1 Clock System Block Diagram Fig. 6-1 shows the clock system diagram. Each clock is defined as follows. fosc1 : Clock input from external high-speed oscillator (X1 and X2) fosc2 : Clock input from internal high-speed oscillator ...

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Clock/Mode Control CGOSCCR<WUEON> CGOSCCR<WUODR13:0> Warm-up timer CGOSCCR <XEN2> CGOSCCR <WUPSEL2:1> Starts oscillation after reset CGOSCCR <OSCSEL> High-speed fosc2 oscillator2 X1 High-speed oscillator1 X2 CGOSCCR <XEN1> OFD Stops oscillation fosc1 after reset XT1 Low-speed oscillator XT2 fs CGOSCCR <XTEN> Stops ...

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Clock Multiplication Circuit (PLL) This circuit outputs the fpll clock that is quadruple of the high-speed oscillator output clock, fosc. This lowers the oscillator input frequency while increasing the internal clock speed. The PLL is disabled after reset is ...

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Clock/Mode Control The following are the examples of the warm-up function configuration. <Example Securing the stability time for the PLL(In case of high-speed oscillator1) > CGOSCCR<WUPSEL1>=”0” CGOSCCR<WUPSEL2>=”1” CGOSCCR<WUPODR13:0>=” warm-up time (1/fosc1)/4”/ CGOSCCR0<WUEON>=”1” CGOSCCR0<WUEF> Read (Note) When high-speed oscillator is ...

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System Clock The TMPM380 offers three selectable system clocks : two high-speed clocks and one low-speed clock. Two kinds of high-speed clocks are selectable either internal oscillator or external oscillator. After reset, internal oscillator is available, and external oscillator ...

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Clock/Mode Control 6.3.5.2 Low speed clock • Input frequency from XT1 and XT2 Input Frequency Range Maximum Operating 30 to 34(kHz) 6.3.6 Prescaler Clock Control Each peripheral function has a prescaler for dividing a clock. As the clock φT0 ...

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Modes and Mode Transitions 6.4.1 Mode Transitions The NORMAL mode and the SLOW mode use the high-speed and low-speed clocks for system clock respectively. The IDLE, SLEEP and STOP modes can be used as the low power consumption mode ...

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Clock/Mode Control 6.5 Operation Modes Two operation modes, NORMAL and SLOW, are available. The features of each mode are described below. 6.5.1 NORMAL Mode This mode is to operate the CPU core and the peripheral hardware by using the ...

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IDLE Mode Only the CPU is stopped in this mode. Each peripheral function has one bit in its control register for enabling or disabling operation in the IDLE mode. When the IDLE mode is entered, peripheral functions for which ...

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Clock/Mode Control Pin Name RESET, MODE control pins X1,XT1 Oscillator X2, XT2 Ports PAx to PPx Debag Interface TMS/SWDIO/TDO/SWV External INT0 to INTF Interrupts SSP SPnCLK/SPnFSS/SPnDO ______________ GEMGn /MTnIN MPT(IGBT) MTnOUTxx ___________ EMGn MPT(PMD) UOn/VOn/WOn/XOn/YOn/ZOn Others ○: Input or ...

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Operational State in Each Mode Table 6-7 show the operational state in each mode. “○” “×” For I/O port, and “○” “×” functions, and indicate that clock is supplied and is not supplied respectively. Table 6-7 Operational State in ...

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Clock/Mode Control 6.5.9 Releasing the Low Power Consumption Mode The low power consumption mode can be released by an interrupt request, NMI or reset. The release source that can be used is determined by the low power consumption mode ...

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Release by reset Any low power consumption modes can be released by reset from the RESET pin. After that, the mode switches to NORMAL and all the registers are initialized as is the case with normal reset. Refer to ...

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Clock/Mode Control 6.5.10 Warm-up Mode transition requires the warm-up so that the oscillator provides stable oscillation. In the mode transition from STOP to NORMAL/ SLOW or from SLEEP to NORMAL, the warm-up counter is activated automatically. And then the ...

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Clock Operations in Mode Transition The clock operations in mode transition are described in the following sections. 6.5.11.1 Transition of operation modes: NORMAL→STOP→NORMAL Before entering to STOP mode, please set warming-up time to CGOSCCR<WUODR[13:0]> and select clock-source that is ...

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Clock/Mode Control 6.5.11.3 Transition of operation modes: SLOW→STOP→SLOW The warm-up is activated automatically necessary to set the warm-up time before entering the STOP mode. WFI instruction / sleep-on-exit SLOW Mode fs Warm-up fsys (System clock = fs) ...

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Exceptions This chapter describes features, types and handling of exceptions. Exceptions have close relation to the CPU core. Refer to “Cortex-M3 Technical Reference Manual” if needed. 7.1 Overview An exception causes the CPU to stop the currently executing process ...

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Exceptions 7.1.2 Handling Flowchart The following shows how an exception/interrupt is handled. indicates hardware handling. Each step is described later in this chapter. Processing Detection by CG/CPU Handling by CPU Branch to ISR Execution of ISR Return from exception ...

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Exception Request and Detection (1) Exception occurrence Exception sources include instruction execution by the CPU, memory accesses, and interrupt requests from external interrupt pins or peripheral functions. An exception by CPU instruction execution is caused when the CPU executes ...

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Exceptions No Exception type 1 Reset Non-Maskable 2 Interrupt 3 Hard Fault Memory Management 4 5 Bus Fault 6 Usage Fault 7-10 Reserved 11 SVCall 12 Debug Monitor 13 Reserved 14 PendSV 15 SysTick 16- External Interrupt (Note 1) ...

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Exception Handling and Branch to the Interrupt Service Routine (Pre-emption) When an exception occurs, the CPU suspends the currently executing process and branches to the interrupt service routine. This is called “pre-emption”. (1) Stacking When the CPU detects an ...

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Exceptions (3) Late-arriving If the CPU detects a higher priority exception before executing the ISR for a previous exception, the CPU handles the higher priority exception first. This is called “late-arriving”. A late-arriving exception causes the CPU to fetch ...

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Executing an ISR An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by the user. An ISR may need to include code for clearing the interrupt request so that the same interrupt will not occur ...

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Exceptions (2) Exception exit sequence When returning from an ISR, the CPU performs the following operations: Pop eight registers Pops the eight registers (PC, xPSR r3, r12 and LR) from the stack and adjust the SP. Load ...

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Reset Exceptions Reset exceptions are generated from the following three sources. Use the Reset Flag (CGRSTFLG) Register of the Clock Generator to identify the source of a reset. ・External reset pin A reset exception occurs when an external reset ...

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Exceptions 7.4 SysTick SysTick provides interrupt features using the CPU’s system timer. In case set a value in the SysTick Reload Value Register and enable the SysTick features in the SysTick Control and Status Register, the counter loads with ...

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Interrupt This chapter describes routes, factors and required settings of interrupts. The CPU is notified of interrupts by each signal of interrupt factor. It sets priority on the interrupts and handles an interrupt request with the highest priority. The ...

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Exceptions 7.5.1.2 Interrupt signal generation An interrupt request signal is generated from an external pin assigned as the interrupt factor or a peripheral IP. ・From external pin Set the port control register so that the external pin can perform ...

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List of Interrupt Factors Table 7-2 shows the list of interrupt factors. Table 7-2 List of Hardware Interrupt Factors (1/2) INT Interrupt factors No. INT0 Interrupt Pin (PH0/AIN0/INT0) 0 INT1 Interrupt Pin (PH1/AIN1/INT1) 1 INT2 Interrupt Pin (PH2/AIN2/INT2) 2 ...

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Exceptions No. INTTB20 16bit TMRB2 compare match detection 0/ Over flow 46 INTTB21 16bit TMRB2 compare match detection 1 47 INTTB30 16bit TMRB3 compare match detection 0/ Over flow 48 INTTB31 49 16bit TMRB3 compare match detection 1 INTCAP20 ...

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Active Level The active level indicates which change in signal of an interrupt factor triggers an interrupt. The CPU recognize an interrupt signal as an interrupt factor when it is changed from “L” to “H”. A signal directly sent ...

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Exceptions 7.5.2 Interrupt handling 7.5.2.1 Flowchart The following shows how an interrupt is handled. indicates hardware handling. Processing Settings for detection Settings for generating interrupt request signal Hardware Interrupt factor is generated Not clearing standby mode Clearing standby mode ...

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Processing The CPU detects the interrupt. Detecting interrupt The CPU handles the interrupt. Handling interrupt Executing interrupt Program for the interrupt service routine. service routine Clear the interrupt factor if needed. Configure to return to the preceding program from the ...

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Exceptions 7.5.2.2 Preparation When preparing for an interrupt needed to pay attention to the order of configuration to avoid any unexpected interrupt on the way. Initiating an interrupt or changing its configuration must be implemented in the ...

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Preconfiguration 1 (Interrupt from external pin) Set “1” to the port function register of the corresponding pin. Setting PnFRx[m] allows the pin to be used as the function pin. Setting PnIE[m] allows the pin to be used as the ...

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Exceptions (6) Enabling interrupt by CPU Enable the interrupt by the CPU as shown below possible to clear the suspended interrupt by writing the Interrupt Clear-Pending register. Then, enable the intended interrupt with the Interrupt Set-Enable register. ...

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Interrupt Service Routine Interrupt service routine requires specific programming according to the application to be used. This section describes what is recommended at the service routine programming and how the factor is cleared. (1) Pushing during interrupt service routine ...

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Exceptions 7.6 Exception/Interrupt-related registers The clock generator registers and their addresses are as shown below. 7.6.1 Register List ●NVIC Resisters SysTick Control and Status Resister SysTick Reload Value Resister SysTick Current Value Resister SysTick Calibration Value Register Interrupt Set-Enable ...

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NVIC Registers 7.6.2.1 SysTick Control and Status Register 7 bit Symbol Read/Write After reset Function 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 bit Symbol Read/Write After reset Function <bit0> <ENABLE> 1 ...

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Exceptions 7.6.2.2 SysTick Reload Value Register 7 bit Symbol Read/Write After reset Function 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 bit Symbol Read/Write After reset Function <bit23:0> <RELOAD> Set the value ...

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SysTick Current Value Register 7 bit Symbol Read/Write After reset Function [Read] Current SysTick timer value [Write] Clear 15 bit Symbol Read/Write After reset Function [Read] Current SysTick timer value [Write] Clear 23 bit Symbol Read/Write After reset Function ...

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Exceptions 7.6.2.4 SysTick Calibration Value Register 7 bit Symbol Read/Write After reset 1 Function 15 bit Symbol Read/Write After reset 0 Function 23 bit Symbol Read/Write After reset 0 Function 31 bit Symbol NOREF Read/Write R After reset 0 ...

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Interrupt Set-Enable Register 1 7 bit Symbol Read/Write After reset 0 Function Interrupt number 7 [Write] 1: Enable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 15 [Write] 1: Enable [Read] 0: ...

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Exceptions 7.6.2.6 Interrupt Set-Enable Register 2 7 bit Symbol Read/Write After reset 0 Function Interrupt number 39 [Write] 1: Enable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 47 [Write] 1: Enable ...

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Interrupt Set-Enable Register 3 7 bit Symbol Read/Write After reset 0 Function Interrupt number 71 [Write] 1: Enable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 79 [Write] 1: Enable [Read] 0: ...

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Exceptions 7.6.2.8 Interrupt Clear-Enable Register 1 7 bit Symbol Read/Write After reset 0 Function Interrupt number 7 [Write] 1: Disable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 15 [Write] 1: Disable ...

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Interrupt Clear-Enable Register 2 7 bit Symbol Read/Write After reset 0 Function Interrupt number 39 [Write] 1: Disable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 47 [Write] 1: Disable [Read] 0: ...

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Exceptions 7.6.2.10 Interrupt Clear-Enable Register 3 7 bit Symbol Read/Write After reset 0 Function Interrupt number 71 [Write] 1: Disable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 79 [Write] 1: Disable ...

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Interrupt Set-Pending Register 1 7 bit Symbol Read/Write After reset Function Interrupt Interrupt number 7 number 6 [Write] [Write] 1: Pend 1: Pend [Read] [Read] 0: Not 0: Not pending pending 1: Pending 1: Pending 15 bit Symbol Read/Write ...

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Exceptions <bit31:0> <SETPEND> Use these bits to force interrupts into the pending state or determine which interrupts are currently pending. Writing “1” bit in this register pends the corresponding interrupt. However, writing “1” has no effect on ...

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Interrupt Set-Pending Register 2 7 bit Symbol Read/Write After reset Function Interrupt Interrupt number 39 number 38 [Write] [Write] 1: Pend 1: Pend [Read] [Read] 0: Not 0: Not pending pending 1: Pending 1: Pending 15 bit Symbol Read/Write ...

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Exceptions <bit31:0> <SETPEND> Use these bits to force interrupts into the pending state or determine which interrupts are currently pending. Writing “1” bit in this register pends the corresponding interrupt. However, writing “1” has no effect on ...

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Interrupt Set-Pending Register 3 7 bit Symbol Read/Write After reset Function Interrupt Interrupt number 71 number 70 [Write] [Write] 1: Pend 1: Pend [Read] [Read] 0: Not 0: Not pending pending 1: Pending 1: Pending 15 bit Symbol Read/Write ...

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Exceptions <bit30:0> <SETPEND> Use these bits to force interrupts into the pending state or determine which interrupts are currently pending. Writing “1” bit in this register pends the corresponding interrupt. However, writing “1” has no effect on ...

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Interrupt Clear-Pending Register 1 7 bit Symbol Read/Write After reset Function Interrupt Interrupt number 7 number 6 [Write] [Write] 1: Clear 1: Clear pending pending interrupt interrupt [Read] [Read] 0: Not 0: Not pending pending 1: Pending 1: Pending ...

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Exceptions <bit31:0> <CLRPEND> Use these bits to clear pending interrupts or determine which interrupts are currently pending. Writing “1” bit in this register clears the corresponding pending interrupt. However, writing “1” has no effect on an interrupt ...

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Interrupt Clear-Pending Register 2 7 bit Symbol Read/Write After reset Function Interrupt Interrupt number39 number 38 [Write] [Write] 1: Clear 1: Clear pending pending interrupt interrupt [Read] [Read] 0: Not 0: Not pending pending 1: Pending 1: Pending 15 ...

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Exceptions <bit31:0> <CLRPEND> Use these bits to clear pending interrupts or determine which interrupts are currently pending. Writing “1” bit in this register clears the corresponding pending interrupt. However, writing “1” has no effect on an interrupt ...

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Interrupt Clear-Pending Register 3 7 bit Symbol Read/Write After reset Function Interrupt Interrupt number 71 number 70 [Write] [Write] 1: Clear 1: Clear pending pending interrupt interrupt [Read] [Read] 0: Not 0: Not pending pending 1: Pending 1: Pending ...

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Exceptions <bit30:0> <CLRPEND> Use these bits to clear pending interrupts or determine which interrupts are currently pending. Writing “1” bit in this register clears the corresponding pending interrupt. However, writing “1” has no effect on an interrupt ...

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Interrupt Priority Registers Each interrupt is provided with eight bits of an Interrupt Priority Register. The following shows the addresses of the Interrupt Priority Registers corresponding to interrupt numbers. 31 0xE000_E400 PRI_3 0xE000_E404 PRI_7 0xE000_E408 PRI_11 0xE000_E40C PRI_15 0xE000_E410 ...

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Exceptions 7 bit Symbol Read/Write After reset Function Priority of interrupt number 0 15 bit Symbol Read/Write After reset Function Priority of interrupt number 1 23 bit Symbol Read/Write After reset Function Priority of interrupt number 2 31 bit ...

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Vector Table Offset Register 7 bit Symbol TBLOFF Read/Write R/W After reset 0 Function Offset value 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 bit Symbol Read/Write After reset Function “0” is ...

Page 103

Exceptions 7.6.2.19 System Handler Priority Registers System Handler Priority Registers have eight bits per each exception. The following shows the addresses of the System Handler Priority Registers corresponding to each exception. 31 0xE000_ED18 PRI_7 0xE000_ED1C PRI_11 (SVCall) 0xE000_ED20 PRI_15 ...

Page 104

System Handler Control and State Register 7 bit Symbol SVCALL ACT Read/Write R/W After reset 0 Function SVCall 0: Inactive 1: Active 15 bit Symbol SVCALL BUSFAU PENDED PENDED Read/Write R/W After reset 0 Function SVCall Bus Fault 0: ...

Page 105

Exceptions <bit0> <MEMFAULTACT> <bit1> <BUSFAULTACT> <bit3> <USGFALTACT> <bit7> <SVCALLACT> <bit8> <MONITORACT> <bit10> <PENDSVACT> <bit11> <SYSTICKACT> <bit12> <USGFAULTPENDED> <bit13> <MEMFAULTPENDED> <bit14> <BUSFAULTPENDED> <bit15> <SVCALLPENDED> <bit16> <MEMFAULTENA> <bit17> <BUSFAULTENA> <bit18> <USGFAULTENA> (Note) Extreme caution is needed to clear or set the ...

Page 106

Clock Generator Registers 7.6.3.1 CG Interrupt Mode Control Register A This resister set the clearing standby request active level of external interrupt INT0~INT3. 7 CGIMCGA bit Symbol 0x4004_0220 Read/Write R After reset 0 “0” is read Active state setting ...

Page 107

Exceptions 7.6.3.2 CG Interrupt Mode Control Register B This resister set the clearing standby request active level of external interrupt INT4~INT7. 7 CGIMCGB bit Symbol 0x4004_0224 Read/Write R After reset 0 “0” is read Active state setting of INT4 ...

Page 108

CG Interrupt Mode Control Register C This resister set the clearing standby request active level of external interrupt INT8~INTB. 7 CGIMCGC bit Symbol 0x4004_0228 Read/Write R After reset 0 Function “0” is read 15 bit Symbol Read/Write R After ...

Page 109

Exceptions 7.6.3.4 CG Interrupt Mode Control Register D This resister set the clearing standby request active level of external interrupt INTC~INTF. 7 CGIMCGD bit Symbol 0x4004_022C Read/Write R After reset 0 Function “0” is read 15 bit Symbol Read/Write ...

Page 110

CG Interrupt Mode Control Register E This resister set the clearing standby request active level of interrupt 7 CGIMCGE bit Symbol 0x4004_0230 Read/Write R After reset 0 Function “0” is read 15 bit Symbol Read/Write R After reset 0 ...

Page 111

Exceptions Be sure to set active state of the Standby clear request, in case the interrupt is enabled for clearing the Standby modes. (Note 1) When using interrupts, be sure to follow the sequence of actions shown below: 1) ...

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CG Interrupt Request Clear Register This resister clear the Interrupt request from INT0~INTF,INTRTC, INTRMCRX. 7 CGICRCG bit Symbol Read/Write After reset Function “0” is read. 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function ...

Page 113

Exceptions 7.6.3.7 NMI Flag Register NMI Flag resister is a resister for reading NMI generation status. CGNMIFLG bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After ...

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Reset Flag Register Reset Flag Resister is a resister for reading internal Reset generation status per generation factors. Since this register is not cleared automatically necceary to write “0” to clear the register. CGRSTFLG 7 bit Symbol ...

Page 115

Input/Output Ports 8.1 Port registers PxDATA : Port data register To read/write port data. PxCR : Output control Register To control enable/disable output enable/disable input, controled by PxIE register. PxFRn : Function control Register To set functions. ...

Page 116

Input/Output Ports 8.2 Port Functions 8.2.1 Port Status in Stop Mode Input and output in Stop mode are enabled/disabled by the CGSTBYCR<DRVE> bit in the Standby Control Register If PxIE or PxCR is enabled with <DRVE>=1, input or output ...

Page 117

Port A (PA0 to PA7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port A performs the serial interface ...

Page 118

Input/Output Ports 7 PA7F2 PAFR2 Bit Symbol (0x4000_000C) Read/Write After reset 0 Function 0:PORT 1 INT8 7 PA7OD PAOD Bit Symbol (0x4000_ 0028) Read/Write After reset Function 7 PA7UP PAPUP Bit Symbol (0x4000_002C) Read/Write After reset Function 7 PA7DN ...

Page 119

Port B (PB0 to PB7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port B performs the debug communication ...

Page 120

Input/Output Ports 7 PB7F1 PBFR1 Bit Symbol (0x4000_0048) Read/Write After reset Function 0:PORT 1:TRST 7 PB7OD PBOD Bit Symbol (0x4000_ 0068) Read/Write After reset Function 7 PB7UP PBPUP Bit Symbol (0x4000_006C) Read/Write After reset Function 7 PB7DN PBPDN Bit ...

Page 121

Port C (PC0 to PC7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the ports C perform the input/output port ...

Page 122

Input/Output Ports 7 PCFR3 Bit Symbol (0x4000_0090) Read/Write After reset Function 7 PC7F4 PCFR4 Bit Symbol (0x4000_0094) Read/Write After reset Function 0:port 1:RX4 7 PCFR5 Bit Symbol (0x4000_0098) Read/Write After reset Function 7 PC7OD PCOD Bit Symbol (0x4000_ 00A8) ...

Page 123

PC7DN PCPDN Bit Symbol (0x4000_00B0 Read/Write After reset 0 Function 7 PC7IE PCIE Bit Symbol (0x4000_00B8) Read/Write After reset 0 Function Port C pull-down control register PC6DN PC5DN PC4DN R Pull-down 0: disabled ...

Page 124

Input/Output Ports 8.2.5 Port D (PD0 to PD6) (Important) TMPM382 (64 pin version) does not implement port D (PD0 to PD6). Please do not use these functions if you use this product. The port general-purpose, 7-bit ...

Page 125

PDFR2 Bit Symbol (0x4000_00CC) Read/Write After reset Function 7 - PDFR3 Bit Symbol (0x4000_00D0) Read/Write After reset 0 Function 7 - PDOD Bit Symbol (0x4000_ 00E8) Read/Write R After reset 0 Function “0” is read PDPUP ...

Page 126

Input/Output Ports 7 PDIE Bit Symbol (0x4000_00F8) Read/Write R After reset Function “0” is read. Port D input enable control register PD6IE PD5IE PD4IE TMPM380/M382 - TMPM380/M382 ...

Page 127

Port E (PE0 to PE7) (Important) TMPM382 (64 pin version) does not implement PE6 and PE7. Please do not use these functions if you use this product. The port general-purpose, 8-bit input/output port. For this port, ...

Page 128

Input/Output Ports 7 PE7F2 PEFR2 Bit Symbol (0x4000_010C) Read/Write R/W After reset 0 Function 0:PORT 1:INT7. 7 PE7OD PEOD Bit Symbol (0x4000_ 0128) Read/Write After reset 0 Function 7 PE7UP PEPUP Bit Symbol (0x4000_012C) Read/Write After reset 0 Function ...

Page 129

Port F (PF0 to PF4) (Important) TMPM382 (64 pin version) does not implement PF2,PF3 and PF4. Please do not use these functions if you use this product. The port general-purpose, 5-bit input/output port. For this port, ...

Page 130

Input/Output Ports 7 - PFFR3 Bit Symbol (0x4000_0150) Read/Write After reset Function 7 - PFOD Bit Symbol (0x4000_0168) Read/Write After reset Function 7 - PFPUP Bit Symbol (0x4000_016C) Read/Write After reset Function 7 - PFPDN Bit Symbol (0x4000_0170) Read/Write ...

Page 131

Port G (PG0 to PG7) (Important) TMPM382 (64 pin version) does not implement port G (PG0 to PG7). Please do not use these functions if you use this product. The port general-purpose, 8-bit input/output port. For ...

Page 132

Input/Output Ports 7 PGFR3 Bit Symbol (0x4000_0190) Read/Write After reset Function 7 PG7OD PGOD Bit Symbol (0x4000_01A8) Read/Write After reset 0 Function 7 PG7UP PGPUP Bit Symbol (0x4000_01AC) Read/Write After reset Function 7 PG7DN PGPDN Bit Symbol (0x4000_01B0) Read/Write ...

Page 133

Port H (PH0 to PH7) The port general-purpose 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port H performs the analog input ...

Page 134

Input/Output Ports 7 PH7OD PHOD Bit Symbol (0x4000_ 01E8) Read/Write After reset Function 7 PH7UP PHPUP Bit Symbol (0x4000_01EC) Read/Write After reset Function 7 PH7DN PHPDN Bit Symbol (0x4000_01F0) Read/Write After reset 0 Function 7 PH7IE PHIE Bit Symbol ...

Page 135

Port I (PI0 to PI1) The port general-purpose, 2-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port I performs the analog input ...

Page 136

Input/Output Ports 7 - PIPUP Bit Symbol (0x4000_022C) Read/Write After reset Function 7 - PIPDN Bit Symbol (0x4000_0230) Read/Write After reset 0 Function 7 - PIIE Bit Symbol (0x4000_0238) Read/Write After reset Function Port I pull-up control register 6 ...

Page 137

Port J (PJ0 to PJ7) (Important) TMPM382 (64 pin version) does not implement port J (PJ0 to PJ7). Please do not use these functions if you use this product. The port general-purpose, 8-bit input/output port. For ...

Page 138

Input/Output Ports 7 PJ7OD PJOD Bit Symbol (0x4000_ 0268) Read/Write After reset Function 7 PJ7UP PJPUP Bit Symbol (0x4000_026C) Read/Write After reset Function 7 PJ7DN PJPDN Bit Symbol (0x4000_0270) Read/Write After reset 0 Function 7 PJ7IE PJIE Bit Symbol ...

Page 139

Port L(PL0, PL2) The port general-purpose 2-bit port that contained 1-bit output port and 1-bit input/output port. For this port, inputs can be specified in units of bits. Besides the general-purpose input function, the port L ...

Page 140

Input/Output Ports 7 - PLOD Bit Symbol (0x4000_ 02E8) Read/Write After reset Function 7 - PLPUP Bit Symbol (0x4000_02EC) Read/Write After reset Function 7 - PLPDN Bit Symbol (0x4000_02F0) Read/Write After reset 0 Function 7 - PLIE Bit Symbol ...

Page 141

Port M (PM0 to PM1) The port general-purpose, 2-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port I performs the high-speed oscillator1 ...

Page 142

Input/Output Ports 7 - PMPUP Bit Symbol (0x4000_032C) Read/Write After reset Function 7 - PMPDN Bit Symbol (0x4000_0330) Read/Write After reset 0 Function 7 - PMIE Bit Symbol (0x4000_0338) Read/Write After reset Function Port M pull-up control register 6 ...

Page 143

Port N (PN0 to PN7) (Important) TMPM382 (64 pin version) does not implement port N (PN0 to PN7). Please do not use these functions if you use this product. The port general-purpose, 8-bit input/output port. For ...

Page 144

Input/Output Ports 7 PN7F2 PNFR2 Bit Symbol (0x4000_034C) Read/Write R/W After reset 0 Function 0:PORT 1:INTE. 7 PN7OD PNOD Bit Symbol (0x4000_ 0368) Read/Write After reset 0 Function 7 PN7UP PNPUP Bit Symbol (0x4000_036C) Read/Write After reset 0 Function ...

Page 145

Port P (PP0 to PP1) The port general-purpose, 2-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port P performs the low-speed oscillator(XT1 ...

Page 146

Input/Output Ports 7 - PPPUP Bit Symbol (0x4000_03AC) Read/Write After reset Function 7 - PPPDN Bit Symbol (0x4000_03B0) Read/Write After reset 0 Function 7 - PPIE Bit Symbol (0x4000_03B8) Read/Write After reset Function Port P pull-up control register 6 ...

Page 147

Appendex (Ports setting) The setting of the registers of each function lists are shown in the following. 8.3.1 Port A setting Port Function Type Name * GPIO - PA0 TB0IN FT1 INT3 FT4 * GPIO - PA1 TB0OUT FT1 ...

Page 148

Input/Output Ports 8.3.2 Port B setting Port Function Type Name * GPIO - PB0 TRACECLK FT1 * GPIO - PB1 TRACEDATA0 FT1 * GPIO - PB2 TRACEDATA1 FT1 * TMS/SWDIO FT2 PB3 GPIO - * TCK/SWCLK FT2 PB4 GPIO ...

Page 149

Port C setting Port Function Type Name * GPIO - UO0 FT3 PC0 SP0DO FT3 SDA0 FT1 SO0 FT1 * GPIO - XO0 FT3 PC1 SP0DI FT1 SCL0 FT1 SI0 FT1 * GPIO - VO0 FT3 SP0CLK (IN) FT3 ...

Page 150

Input/Output Ports 【Function】 *: Initial state 【PCFRn】 "0": All the corresponding bits of the PCFRn registers are not selected. "PCxFn": The bits of the PCFRn registers should be selected are described by the bit 【 Common setting in Port ...

Page 151

Port D setting Port Function Type Name PD0 * GPIO - ENCA0 FT1 TB5IN FT1 INTC FT4 PD1 * GPIO - ENCB0 FT1 TB5OUT FT1 PD2 * GPIO - ENCZ0 FT1 INTD FT4 PD3 * GPIO - INT9 FT4 ...

Page 152

Input/Output Ports 8.3.5 Port E setting Port Function Type Name * GPIO - PE0 TX0 FT1 * GPIO - PE1 RX0 FT1 * GPIO - SCLK0 (IN) FT1 PE2 SCLK0 (OUT) FT1 CTS0 FT1 * GPIO - PE3 TB4OUT ...

Page 153

Port F setting Port Function Type Name * GPIO - PF0 TB7IN FT1 * GPIO - PF1 TB7OUT FT1 ALARM FT1 * GPIO - ENCA1 FT1 PF2 SCLK3 (IN) FT1 SCLK3 (OUT) FT1 CTS3 FT1 * GPIO - PF3 ...

Page 154

Input/Output Ports 8.3.7 Port G setting Port Function Type Name * GPIO - UO1 FT3 PG0 SDA1 FT1 SO1 FT1 * GPIO - XO1 FT3 PG1 SCL1 FT1 SI1 FT1 * GPIO - VO1 FT3 PG2 SCK1 (IN) FT1 ...

Page 155

Port H setting Port Function Type Name * GPIO - PH0 INT0 FT4 AIN0 FT5 * GPIO - PH1 INT1 FT4 AIN1 FT5 * GPIO - PH2 INT2 FT4 AIN2 FT5 * GPIO - PH3 AIN3 FT5 * GPIO ...

Page 156

Input/Output Ports 8.3.9 Port I setting Port Function Type Name * GPIO - PI0 AIN8 FT5 * GPIO - PI1 AIN9 FT5 【Function】 *: Initial state 【PIFR1】 "0": All the corresponding bits of the PIFR1 registers are not selected. ...

Page 157

Port J setting Port Function Type Name * GPIO - PJ0 AIN10 FT5 * GPIO - PJ1 AIN11 FT5 * GPIO - PJ2 AIN12 FT5 * GPIO - PJ3 AIN13 FT5 * GPIO - PJ4 AIN14 FT5 * GPIO ...

Page 158

Input/Output Ports 8.3.11 Port L setting Port Function Type Name * GPIO - PL0 BOOT FT6 * GPIO - PL2 INTF FT4 【Function】 *: Initial state ●: The function that becomes effective for reset. When the external interrupt input ...

Page 159

Port N setting Port Function Type Name * GPIO - PN0 SP1DO FT3 * GPIO - PN1 SP1DI FT1 * GPIO - PN2 SP1CLK (IN) FT3 SP1CLK (OUT) FT3 * GPIO - PN3 SP1FSS (IN) FT3 SP1FSS (OUT) FT3 ...

Page 160

Input/Output Ports 8.3.14 Port P setting Port Function Type Name * GPIO - PP0 XT1 FT5 * GPIO - PP1 XT2 FT5 【Function】 *: Initial state 【PPFRn】 -: There is no corresponding bit. 【Port P SFR 共通】 "0": The ...

Page 161

Port Section Equivalent Circuit Schematics The setting of the registers of each function list is shown in the following. 8.4.1 Port type FT1 <I/O> SCLKn/SCKn/SCLn/SDAn <In> TBnIN/RXn/CTSn/Sin/SPnDI/RXIN/EMGn <Out> TBnOUT/TXn/Son/SCOUT/ALARM Powe-On Reset(UB) Drive Disable In STOP Mode PxPUP (Pull-up Control) ...

Page 162

Input/Output Ports 8.4.2 Port type FT2 <I/O> TMS/SWDIO --------------- <In> TCK/SWCLK/TDI/TRST <Out> TDO/SWV+Pio Powe-On Reset(UB) Drive Disable In STOP Mode PxPUP (Pull-up Control) PxPDN (Pull-down Control) PxCR (Output Control) Function Output Enable PxFRn (Function Control) Function Output PxDATA (Output ...

Page 163

Port type FT3 <I/O> SPnCLK/SPnFSS <Out> SPnDO/UOn/VOn/WOn/YOn/ZOn/MTOUT0n/MTOUT1n Powe-On Reset(UB) Drive Disable In STOP Mode PxPUP (Pull-up Control) PxPDN (Pull-down Control) PxCR (Output Control) Function Output Enable PxFRn (Function Control) Function Output PxDATA (Output Latch) PxOD (Open Drain Control) PxIE ...

Page 164

Input/Output Ports 8.4.4 Port type FT4 <In> INTn Powe-On Reset(UB) Drive Disable In STOP Mode PxPUP (Pull-up Control) PxPDN (Pull-down Control) PxCR (Output Control) PxFRn (Function Control) PxDATA (Output Latch) PxOD (Open Drain Control) PxIE (Input Control) Port Read ...

Page 165

Port type FT5 <In> AINn/Xn/XTn Powe-On Reset(UB) Drive Disable In STOP Mode PxPUP (Pull-up Control) PxPDN (Pull-down Control) PxCR (Output Control) PxDATA (Output Latch) PxOD (Open Drain Control) PxIE (Input Control) Port Read 0 1 AINn, Xn, XTn Figure ...

Page 166

Input/Output Ports 8.4.6 Port type FT6 ---------------- <In> BOOT Powe-On Reset(UB) Drive Disable In STOP Mode PxPUP (Pull-up Control) PxPDN (Pull-down Control) PxCR (Output Control) PxDATA (Output Latch) PxOD (Open Drain Control) BOOT Figure 8-6 Port Type FT6 TMPM380/M382 ...

Page 167

Timer/Event Counters (TMRBs) Important Neither TB3IN,TB3OUT,TB5IN nor TB5OUT are allocated in TMPM382 (64-pin version). Please do not use the function (Up-counter source clock selection and capture operation that uses terminal TB3IN / TB5IN, Timer flip-flop output that uses ...

Page 168

Timer/Event Counters (TMRBs) 9.2 Specification differences among channels Channels (TMRB0 through TMRB7) operate independently and the functions are same except the differences as shown in Table 9-1 to Table 9-3. Therefore, the operational descriptions here are explained only ...

Page 169

Table 9-3 Differences in the Specifications of TMRB Modules (3) Specification Capture interrupt Channel TMRB0 TMRB1 TMRB2 TMRB3 TMRB4 TMRB5 TMRB6 TMRB7 TMPM380/M382 - Interrupt TMRB interrupt INTCAP00 INTTB00 INTCAP01 INTTB01 INTCAP10 INTTB10 INTCAP11 INTTB11 INTCAP20 ...

Page 170

Timer/Event Counters (TMRBs) 9.3 Configuration Each channel consists of a 16-bit up-counter, two 16-bit timer registers (one of which is double-buffered), two 16-bit capture registers, two comparators, a capture input control, a timer flip-flop and its associated control ...

Page 171

Fig 9-2 TMRB3 Block Diagram (the same applies to channel 5) for TMPM382 Because the TMRB3 and the TMRB5 of TMPM382 (64 pins) have no external input pins (TBxIN), the TB2OUT is the only capture trigger signal. The timer flip-flop ...

Page 172

Timer/Event Counters (TMRBs) 9.4 Registers 9.4.1 TMRB registers Table 9-4 shows the register names and addresses of each channel. Channel Specification Timer enable register TB0EN Timer RUN register TB0RUN 0x4001_0004 TB1RUN 0x4001_0044 TB2RUN 0x4001_0084 TB3RUN 0x4001_00C4 Timer control ...

Page 173

TMRBn enable register (channels 0 through 7) 31 TBnEN bit Symbol (0x4001_0xx0) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol TBEN Read/Write R/W ...

Page 174

Timer/Event Counters (TMRBs) 9.4.1.2 TMRB RUN register (channels 0 through 7) 31 bit Symbol TBnRUN (0x4001_0xx4) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 ...

Page 175

TMRB control register (channels 0 through 7) 31 bit Symbol TBnCR (0x4001_0xx8) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol TBWBF Read/Write R/W ...

Page 176

Timer/Event Counters (TMRBs) <TBWBF>:Controls the enabling/disabling of double buffering. 0: Disable Double Buffer. 1: Enable Double Buffer. (Note) TBnCR resister must not be changed during Timer operation (TBnRUN<TBRUN>=1) TMPM380/M382 - TMPM380/M382 ...

Page 177

TMRB mode register (channels 0 thorough 7) 31 TBnMOD bit Symbol (0x4001_0xxC) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R 0 After reset 7 bit Symbol Read/Write R After ...

Page 178

Timer/Event Counters (TMRBs) <TBCPM1:0>:Specifies TMRBn capture timing. “00”: Capture disable “01”: Takes count values into capture register 0 (TBnCP0) upon rising of TBnIN pin input. “10”: Takes count values into capture register 0 (TBnCP0) upon rising of TBnIN ...

Page 179

TMRB flip-flop control register (channels 0 through 7) 31 bit Symbol TBnFFCR (0x4001_0xx0) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol Read/Write After ...

Page 180

Timer/Event Counters (TMRBs) <TBC1T1>:Reverses the timer flip-flop when the up-counter value is taken into the capture register 1 (TBnCP1). 0: TBnFF0 not reverse 1: TBnFF0 reverse (Note) TBnFFCR register must not be changed during Timer operation (TBnRUN<TBRUN> =”1”) ...

Page 181

TMRB status register (channels 0 through 7) 31 bit Symbol TBnST (0x4001_0xx4) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol Read/Write After reset ...

Page 182

Timer/Event Counters (TMRBs) 9.4.1.7 TMRB interrupt mask register (channels 0 through 7) 31 TBnIM bit Symbol (0x4001_0xx8) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 ...

Page 183

TMRB read capture register (channels 0 through 7) 31 TBnUC bit Symbol (0x4001_0xxC) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol TBUC15 Read/Write After reset Function 7 bit Symbol TBUC7 Read/Write ...

Page 184

Timer/Event Counters (TMRBs) 9.4.1.9 TMRB timer register (channels 0 through 7) 31 TBnRG0 bit Symbol (0x4001_0xx0) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol TBRG015 Read/Write After reset Function 7 ...

Page 185

TMRB capture register (channels 0 through 7) 31 bit Symbol TBnCP0 (0x4001_0xx8) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol TBCP015 Read/Write After reset Function 7 bit Symbol TBCP07 Read/Write After ...

Page 186

Timer/Event Counters (TMRBs) 9.5 Description of Operations for Each Circuit The channels operate in the same way, except for the differences in their specifications as shown in Table 9-1 to Table 9-3. Therefore, the operational descriptions here are ...

Page 187

Table 9-5 Prescaler Output Clock Resolutions @fc = 40MHz Clear peripheral Clock gear Prescaler clock clock value selection <FPSEL> <GEAR2:0> <PRCK2:0> 000(fperiph/1) 001(fperiph/2) 010(fperiph/4) 000 (fc) 011(fperiph/8) 100(fperiph/16) 101(fperiph/32) 000(fperiph/1) 001(fperiph/2) 010(fperiph/4) 100(fc/2) 011(fperiph/8) 100(fperiph/16) 101(fperiph/32) 0 (fgear) 000(fperiph/1) 001(fperiph/2) ...

Page 188

Timer/Event Counters (TMRBs) The prescaler output clock φTn must be selected as φTn<fsys. (φTn is slower than (Note 1) fsys). (Note 2) Do not change the clock gear while the timer is operating. (Note 3) “⎯“ denotes a ...

Page 189

Up-counter (UC0) UC0 is a 16-bit binary counter. • Source clock UC0 source clock, specified by types φT1, φT4 and φT16 of prescaler output clock or the external clock of the TB0IN pin. • Count start/ stop Counter operation ...

Page 190

Timer/Event Counters (TMRBs) 9.5.3 Timer registers (TB0RG0, TB0RG1) TB0RG0 and TB0RG1 are registers for setting values to compare with up-counter values and two registers are built into each channel. If the comparator detects a match between a value ...

Page 191

Capture Registers (TB0CP0, TB0CP1) These are 16-bit registers for latching values from the UC0 up-counter. To read data from the capture register, use a 16-bit data transfer instruction or read in the order of low-order bits followed by high-order ...

Page 192

Timer/Event Counters (TMRBs) 9.6 Description of Operations for Each Mode 9.6.1 16-bit Interval Timer Mode -Generating interrupts at periodic cycles To generate the INTTB01 interrupt, specify a time interval in the TB0RG1 timer register. Same as TB0RG0, INTTB01 ...

Page 193

Programmable Square Wave Output Mode (PPG) Square waves with any frequency and any duty (programmable square waves) can be output. The output pulse can be either low-active or high-active. Programmable square waves can be output from the TB0OUT ...

Page 194

Timer/Event Counters (TMRBs) The block diagram of this mode is shown below. Selector TB0IN φT1 φT4 φ T16 Selector TB0RG0-W R TB0CR<TB0WBF> Each register in the 16-bit PPG output mode must be programmed as listed below. 7 ← ...

Page 195

External trigger Programmable Square Wave Output Mode (PPG) Using an external count start trigger enables one-shot pulse generation with a short delay. (1) The 16-bit up-counter (UC0) is programmed to count up on the rising edge of the TB0IN ...

Page 196

Timer/Event Counters (TMRBs) 9.6.5 Synchronous Timer Mode Taking the synchronization of the start between timers by using the timer synchronous mode becomes possible possible to apply it to the drive such as motors by using the ...

Page 197

Application example using the Capture Function The capture function can be used to develop many applications, including those described below: (1) One-shot pulse output triggered by an external pulse (2) Frequency measurement (3) Pulse width measurement ( 1 ) ...

Page 198

Timer/Event Counters (TMRBs delay is not required, TB0FF0 is reversed when data is taken into TB0CP0, and TB0RG1 is set to the sum of the TB0CPO value (c) and the one-shot pulse width (p ...

Page 199

Frequency ( 2 ) measurement The frequency of an external clock can be measured by using the capture function. To measure frequency, another 16-bit timer is used in combination with the 16-bit event counter mode example, we explain ...

Page 200

Timer/Event Counters (TMRBs Pulse width measurement By using the capture function, the “H” level width of an external pulse can be measured. Specifically, by putting free-running state using the prescaler output clock, ...

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