TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 484

no-image

TMPM382FSFG

Manufacturer Part Number
TMPM382FSFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM382FSFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
64K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
64
Package
QFP(14x14)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
1
I2c/sio (ch)
1
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
10
16-bit Timer / Counter
6
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
16 Remote control signal preprocessor (RMC)
Data reception completed by detecting the max data bit cycle
16.3 Operation Description
Waiting for
16.3.1 Reception of Remote Control Signal
leader
16.3.1.1
16.3.1.2
falling edge cycle, the data bit is determined as 0 or 1. By detecting a leader while RMC is waiting for
a leader, a leader detection interrupt is generated, and the data bit reception starts. The data bit is
determined as 0 or 1 based on a falling edge cycle. RMC is capable of receiving data up to 72bit.
Reception is completed by detecting either a maximum data bit cycle or the excess low width. On
completion of reception, RMC is waiting for the next leader, and the Remote Control Receive Data
Buffer Registers and the Remote Control Receive Status Register are updated.
A remote control signal is sampled by low-speed clock (fs).
RMC starts to receive a data bit if a leader is detected while RMC is waiting for a leader. Based on a
Detecting leader
Sampling Clock
Basic Operation
TMPM380/M382 - 14 / 25 -
Capable of receiving
data up to 72bits
Maximum data bit cycle interrupt
Specified period of a maximum
data bit cycle
TMPM380/M382
Waiting for
leader

Related parts for TMPM382FSFG