TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 478

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

16 Remote control signal preprocessor (RMC)
16.2.8 Remote Control Receive Control Register 2 [RMCRCR2]
<RMCLIEN>:
<RMCEDIEN>:
<RMCLD>:
<RMCPHM>:
<RMCLL7:0>:
<RMCDMAX7:0>:
Read/Write
Read/Write
Read/Write
Read/Write
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
Function
Function
Function
Function
Enables to generate a leader detection interrupt by detecting a leader.
Enables to generate a remote control input falling edge Interrupt.
Enables RMC to receive signals with or without a leader.
Specifies data reception mode of a phase method. If you use the phase method of
which signal cycle is fixed, set “1”.
Specifies an excess low width. If an excess low width is detected, reception is
completed and an interrupt is generated. The low width is not detected if
<RMCLL7:0> = 0y11111111. Calculating formula of an excess low width:
RMCLLx1/fs[s].
Specifies a threshold for detecting a maximum data bit cycle. It is detected when a
data bit cycle exceeds the threshold. It is not detected when <RMCMAX7:0> =
0y11111111. Calculating formula of the threshold: RMCDMAX x 1/fs[s].
Leader
detection
interrupt
0: Not
generated
１:
Generated
Excess low width that triggers reception completion and interrupt generation
0y00000000~0y11111110:RMCLL×1/fs[s]
0y11111111:not to use as the trigger
Maximum data bit cycle that triggers reception completion and interrupt generation
0y00000000~0y11111110:RMCDMAX×1/fs[s]
0y11111111: not to use as the trigger
RMCLIEN RMCEDIE
RMCDMA
RMCLL7
R/W
31
23
15
X7
―
7
0
Remote
control
input
falling
edge
interrupt
0: Not
generated
１:
Generated
TMPM380/M382 - 8 / 25 -
RMCDMA
RMCLL6
R/W
30
22
14
X6
―
N
6
0
”0” is read.
RMCDMA
RMCLL5
29
21
13
X5
―
―
5
RMCDMA
RMCLL4
28
20
12
X4
―
―
4
”0” is read.
R/W
R/W
R
0
R
0
1
1
RMCDMA
RMCLL3
27
19
11
X3
―
―
3
RMCDMA
RMCLL2
26
18
10
X2
―
―
2
Receiving
remote
control
signal with
or without
leader
0: Disable
1: Enable
RMCDMA
RMCLL1
RMCLD
TMPM380/M382
R/W
25
17
X1
―
9
1
0
Receive a
remote
control
signal in
phase
method?
0: No
(receive in
cycle
method)
1:Yes
RMCPHM
RMCDMA
RMCLL0
R/W
24
16
―
X0
8
0
0