TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 23

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

3
3.1
3.2
3.3
3.4
Processor Core
core). For information on the operations of this processor core, please refer to the “Cortex-M3
Technical Reference Manual” issued by ARM Limited. This chapter describes the functions unique to
the TX03 series that are not explained in that document.
information on each revision, see the documents issued by ARM Limited.
TMPM380/M382 does not support
instruction.
TMPM380/M382 does not support SLEEPDEEP.
Processor Core
Configurable Opions
Event
SLEEPDEEPl
The TX03 series has a high-performance 32-bit processor core (the ARM Cortex-M3 processor
The following table shows the revision of the processor core in the TMPM380/M382. For further
The Cortex-M3 core has the optional blocks. The optional blocks of the revision r2p0 are below;
O: Implement
X: Not implement
Optional block
FPB
DWT
ITM
MPU
ETM
AHB-AP
AHB trace macro-cell interface
TPIU
WIC
Product Name
TMPM380
TMPM382
TM
TMPM380/M382 - 1 / 2-
event input/output. Do not use SEV instruction and WFE
Core Revision
r2p0-00rel0
r2p0-00rel0
Implementation
O
O
O
O
O
O
O
X
X
TMPM380/M382