TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 197

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

9.7
Count clock
(Presc aler output clock)
TB0IN pin input
(External trigger pulse)
Match with TB0RG0
Match with TB0RG1
Timer output TB0OUTpin
( 1 ) One-shot pulse output triggered by an external pulse
The capture function can be used to develop many applications, including those described below:
One-shot pulse output triggered by an external pulse is carried out as follows:
The 16-bit up-counter is made to count up by putting it in a free-running state using the prescaler
output clock. An external pulse is input through the TB0IN pin. A trigger is generated at the rising of
the external pulse by using the capture function and the value of the up-counter is taken into the
capture registers (TB0CP0).
The CPU must be programmed so that an interrupt INTCAP00 is generated at the rising of an
external trigger pulse. This interrupt is used to set the timer registers (TB0RG0) to the sum of the
TB0CP0 value (c) and the delay time (d), (c + d), and set the timer registers (TB0RG1) to the sum of
the TB0RG0 values and the pulse width (p) of one-shot pulse, (c + d + p).
TB0RG1 change must be completed before the next match.
In addition, the timer flip-flop control registers (TB0FFCR<TBE1T1, TBE0T1>) must be set to “11.”
This enables triggering the timer flip-flop (TB0FF0) to reverse when UC0 matches TB0RG0 and
TB0RG1. This trigger is disabled by the INTTB01 interrupt after a one-shot pulse is output.
Symbols (c), (d) and (p) used in the text correspond to symbols c, d and p in Fig 9-6 One-shot Pulse
Output (With Delay).”
Application example using the Capture Function
(2) Frequency measurement
(1) One-shot pulse output triggered by an external pulse
(3) Pulse width measurement
Note: The value of TBnRG0/1 must be set as TBnRG0 < TBnRG1 in PPG mode.
Fig 9-6 One-shot Pulse Output (With Delay)
c
Put the counter in a free-running state.
Disable reverse when
data is taken into CAP0
Taking data into the capture register (TB0CP0)
INT CAP00 generation
Delay time
TMPM380/M382 - 31 / 34 -
Enable reverse
(d)
c + d
Enable
reverse
INTTB00
Pulse width
(p)
c + d + p
INTTB01 generation
TMPM380/M382