TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 341
TMPM382FSFG
Manufacturer Part Number
TMPM382FSFG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM380FWDFG.pdf
(700 pages)
Specifications of TMPM382FSFG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
64K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
64
Package
QFP(14x14)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
1
I2c/sio (ch)
1
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
10
16-bit Timer / Counter
6
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
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(1) When <P3EN> = 1 (<EN0INT> = 0x0002)
(2) When <P3EN> = 0 (<EN0INT> = 0x0002)
Capture Register, EN0CNT
Revolution Error, REVERR
Capture Register, EN0CNT
Encoder Pulse, ENCLK
Revolution Error, REVERR
Encoder Pulse, ENCLK
12.3.1.3
Encoder Counter
Encoder Counter
・ During CCW rotation, the encoder counter counts down; when it has reached 0x0000, it wraps
・ When <ENCLR> is set to 1, causing the internal counter to be cleared to 0.
Interrupt, INTENC0
Interrupt, INTENC0
・ In Sensor Timer Count mode, the Hall sensor inputs of the TMPM370 should be connected to the
・ The encoder counter always counts up; it is cleared to 0 on ENCLK. When the encoder counter
Rotation Direction
Rotation Direction
Encoder Input, A
Encoder Input, B
Encoder Input, Z
Encoder Input, A
Encoder Input, B
Encoder Input, Z
・
・
・
・
(÷2) TIMPLS
(÷2) TIMPLS
around to 0xFFFF on the next ENCLK.
A(U), B(V) and Z(W) channels. The encoder counter measures the interval between two
contiguous pulses of ENCLK, which is either multiplied_by_4 clock (when <P3EN> = 0) derived
from the decoded A(U) and B(V) signals or multiplied_by_6 clock (when <P3EN> = 1) derived
from the decoded A(U), B(V) and Z(W) signals.
<U/D> is set to 1 during CW rotation and cleared to 0 during CCW rotation.
TIMPLS, which is derived by dividing ENCLK by a programmed factor, can be driven out
externally.
If <CMPEN> is set to 1, an interrupt is generated when the value of the internal counter has
reached the value of <EN0INT>.
Clearing <ENRUN> to 0 clears <U/D> to 0.
Sensor Timer Count Mode
fsys
fsys
dir
dir
1
1
0 (ini)
0 (ini)
2
2
3
3
0
0
1
1
2
2
TMPM380/M382 - 15 / 23 -
3
3
0
0
3
3
1
1
CW
CW
2
2
3
3
0
0
1
1
2
2
3
3
2
2
3
3
3
3
0
0
1
1
2
2
0
0
1
1
2
2
2
2
3
3
0
0
1
1
CCW
CCW
2
2
3
3
TMPM380/M382
0
3
0
3
1
1
2
2
3
3
0
0
1
1
2
2
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