TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 584

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TMPM382FSFG

Manufacturer Part Number
TMPM382FSFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM382FSFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
64K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
64
Package
QFP(14x14)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
1
I2c/sio (ch)
1
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
10
16-bit Timer / Counter
6
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
(6) Operation of Boot Program
When Single Boot mode is selected, the boot program is automatically executed on startup. The
boot program offers these two commands, of which the details are provided on the following
subsections. The addresses described in this section are the virtual unless otherwise noted.
1.
2. Chip and Protection Bit Erase command
This command serves to recover boot programming operation when a user forgets the
RAM Transfer command
The RAM Transfer command stores program code transferred from a host controller to the
on-chip RAM and executes the program once the transfer is successfully completed. The
user program RAM space can be assigned to the range from 0x2000_0400 to the end
address of RAM, whereas the boot program area (0x2000_0000 to 0x2000_03FF) is
unavailable. The user program starts at the assigned RAM address.
The RAM Transfer command can be used to download a flash programming routine of your
own; this provides the ability to control on-board programming of the flash memory in a
unique manner. The programming routine must utilize the flash memory command
sequences described in Section20.3.
coming from the controller against that stored in the flash memory.
This command erases the entire area of the flash memory automatically without verifying a
password. All the blocks in the memory cell and their protection conditions are erased even
when any of the blocks are prohibited from writing and erasing. When the command is
completed, the SECBIT <SECBIT> bit is set to “1”.
password. Therefore password verification is not executed.
Before initiating a transfer, the RAM Transfer command verifies a password sequence
TMPM380/M382 - 23 / 54 -
TMPM380/M382

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