TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 372

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

Note: To switch the I/O interface SCLK output mode to other modes, read the SCxCR register
2.
3. Framing error <FERR>: Bit 2 of the SC0CR register
and clear the under-run flag.
Parity error/under-run error <PERR>: Bit 3 of the SC0CR register
In the UART mode, this bit is set to “1” when a parity error is generated. A parity error is
generated when the parity generated from the received data is different from the parity
received. This flag is set to “0” when it is read.
In the I/O interface mode, this bit indicates an under-run error. When the double buffer
control bit <WBUF> of the serial mode control register SC0MOD2 is set to “1” in the
SCLK input mode, if no data is set to the transmit double buffer before the next data
transfer clock after completing the transmission from the transmit shift register, this
error flag is set to “1” indicating an under-run error. If the transmit FIFO is enabled, any
data content in the transmit FIFO will be moved to the buffer. When the transmit FIFO
and the double buffer are both empty, an under-run error will be generated. Because
no under-run errors can be generated in the SCLK output mode, this flag is inoperative
and the operation is undefined. If Transmit Buffer is disabled, the under-run flag
<PERR> will not be set. This flag is set to “0” when it is read.
In the UART mode, this bit is set to “1” when a framing error is generated. This flag is
set to “0” when it is read. A framing error is generated if the corresponding stop bit is
determined to be “0” by sampling the bit at around the center. Regardless of the
<SBLEN> (stop bit length) setting of the serial mode control register 2, SC0MOD2, the
stop bit status is determined by only 1 bit on the receive side.
Operation mode
UART
I/O Interface
(SCLK input)
I/O Interface
(SCLK output)
TMPM380/M382 - 23 / 52 -
Error flag
OERR
PERR
FERR
OERR
PERR
FERR
OERR
PERR
FERR
Function
Fixed to 0 (WBUF = 0)
Fixed to 0
Operation undefined
Operation undefined
Fixed to 0
Overrun error flag
Parity error flag
Framing error flag
Overrun error flag
Underrun error flag (WBUF = 1)
TMPM380/M382