TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 443

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

15 Serial Bus Interface (I2C/SIO)
15.5 Control in the I2C Bus Mode
15.5.1 Setting the Acknowledgement Mode
15.5.2 Setting the Number of Bits per Transfer
15.5.3 Serial Clock
Setting SBInCR1<ACK> to “1” selects the acknowledge mode. When operating as a master,
the SBI adds one clock for acknowledgment signals. As a transmitter, the SBI releases the
SDA pin during this clock cycle to receive acknowledgment signals from the receiver. As a
receiver, the SBI pulls the SDA pin to the “L” level during this clock cycle and generates
acknowledgment signals.
By setting <ACK> to “0”, the non-acknowledgment mode is activated. When operating as a
master, the SBI does not generate clock for acknowledgement signals.
SBInCR1 <BC2:0> specifies the number of bits of the next data to be transmitted or
received.
Under the start condition, <BC2:0> is set to “000,” causing a slave address and the direction
bit to be transferred in a packet of eight bits. At other times, <BC2:0> keeps a previously
programmed value.
(Note)
t
t
fscl = 1/(t
Clock source
SBInCR1 <SCK2:0> specifies the maximum frequency of the serial clock to be output
from the SCL pin in the master mode.
LOW
HIGH
=
= 2
= 2
2
n-1
n-1
n
fsys
Low
+ 72
/fsys + 58/ fsys
The highest speeds in the standard and high-speed
modes are specified to 100kHz and 400kHz respectively
following the communications standards. Note that the
internal SCL clock frequency is determined by the fsys
used and the calculation formula shown above.
/ fsys + 14/ fsys
+ t
t
HIGH
TMPM380/M382 - 14 / 41 -
HIGH
)
Fig 15-8 Clock Source
t
LOW
SBInCR1 <SCK2:0>
000
001
010
011
100
101
110
1/fscl
10
11
n
5
6
7
8
9
TMPM380/M382