TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 390

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

TMPM380/M382
SCLK input mode
In the SCLK input mode, if SC0MOD2 <WBUF> is set to “0” and the transmit double
buffers are disabled, 8-bit data that has been written in the transmit buffer is output
from the TXD0 pin when the SCLK0 input becomes active. When all 8 bits are sent, the
INTTX0 interrupt is generated. The next transmit data must be written before the
timing point “A” as shown in Fig 13-11.
If SC0MOD2 <WBUF> is set to “1” and the transmit double buffers are enabled, data is
moved from Transmit Buffer to Transmit shift register when the CPU writes data to
Transmit Buffer before the SCLK0 becomes active or when data transmission from
Transmit shift register is completed. As data is moved from Transmit Buffer to Transmit
shift register, the transmit buffer empty flag SC0MOD2 <TBEMP> is set to “1” and the
INTTX0 interrupt is generated. If the SCLK0 input becomes active while no data is in
Transmit Buffer, although the internal bit counter is started, an under-run error occurs
and 8-bit dummy data (FFh) is sent.
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