TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 493

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

Remote control signal
waveform (input from pin)
Reversed remote control
signal waveform
16.3.1.9
waveform only has low width. This signal starts with a leader that only has low width and a data bit
cycle starts from the rising edge. To enable the signal, it must be sent after being reversed by setting
the RMCRCR4 <RMCPO> bit to “1”. This is because RMC is configured to detect a data bit cycle from
the falling edge.
the rule shown below.
<RMCDATL6:0> bit.
Control Register 2.
RMCRCR2 <RMCDMAX7:0> bits. To complete reception by detecting the low width, you need to
configure the RMCRCR2 <RMCLL7:0> bits. Detecting the maximum data bit cycle or the excess low
width completes reception and generates an interrupt. RMC waits for the next leader.
Waiting for a leader
The figure shown below illustrates a remote control signal that starts with a leader of which
A leader is detected by the low width. When you configure the RMCRCR1 register, you must follow
<RMCLLMAX7:0> = 0y00000000
<RMCLCMAX7:0> > <RMCLCMIN7:0>
If the rules are applied, RMC does not care about the value of <RMCLLMIN7:0>.
To determine the data bit as 0 or 1, configure a threshold of the determination with the RMCRCR3
Configure a maximum data bit cycle with the <RMCDMAX7:0> bits of the Remote Control Receive
To complete reception by detecting the maximum data bit cycle, you need to configure the
A Leader only with Low Width
Leader
TMPM380/M382 - 23 / 25 -
Leader
interrupt
Detecting maximum data bit cycle completes
reception.
detection
Final bit
Low period
TMPM380/M382
Waiting for a leader
Low width detection
interrupt