TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 320

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

11.4 Operation Descriptions
11.4.1 Analog Reference Voltages
11.4.2 Starting AD Conversion
ongoing program and start AD conversion correspond to PMD trigger number.
handled after the ongoing program is completed.
trigger. The following timing chart and table show the delay.
in ADC. There are no registers for controlling current between AVDD5 and AVSS. Inputs to these
pins are fixed.
enables the ADMOD3 register.
register0 (ADxREG0)
register1 (ADxREG1)
AD conversion result
AD conversion result
AD conversion is started by software or one of the following three trigger signals.
These start triggers are given priorities as shown below.
・ PMD trigger (See “11.3.5 PMD Trigger Program Registers”)
・ Timer trigger (TMRB5) (See “11.3.6 Timer Trigger Program Registers”)
・ Software trigger (See “11.3.7 Software Trigger Program Registers”）
For the High-level and Low-level analog reference voltages, the AVDD5 and AVSS pins are used
The ADC can decrease the current consumption when stopping. Setting the <RCUT> to “1”
Note : Analog input pins also use input/output ports(port H/ I/ J), it is recommended for the
If the PMD trigger occurs while an AD conversion is in progress, the PMD trigger is handled stop the
If a higher-priority trigger occurs while an AD conversion is in progress, the higher-priority trigger is
It has some delay from generation of trigger to start of AD conversion. The delay depends on the
PMD trigger 0 >
Busy flag
Trigger
ADBFN
purpose of maintaining the accuracy of AD conversion result that do not execute
input/output instructions during AD conversion. Additionally, do not input widely varying
signals into the ports adjacent to analog input pins.
Delay time from trigger
Fig 11.2 Figure Timing chart of A/D conversion
>PMD trigger 3 > Timer trigger > Software trigger > constant trigger
1st conversion
TMPM380/M382 - 33 / 39 -
AD conversion time
Delay time to the next
conversion
Result of 1st conversion
2nd conversion
AD conversion time
TMPM380/M382
Result of 2nd conversion