TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 603

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

23 Flash Memory Operation
2) Automatic chip erase
3)
(Note) Software reset becomes ineffective in bus write cycles on and after the fourth
When multiple pages are to be written, it is necessary to execute the page programming
The automatic chip erase operation starts when the sixth bus write cycle of the command
cycle is completed.
The automatic block erase operation starts when the sixth bus write cycle of the command
cycle is completed.
When a single page has been command written normally terminating the automatic page
writing process, the FLCS [0] <RDY/BSY> bit is set to "1" and it returns to the read mode.
command for each page because the number of pages to be written by a single execution of
the automatic page program command is limited to only one page. It is not allowed for
automatic page programming to process input data across pages.
Data cannot be written to a protected block. When automatic programming is finished, it
automatically returns to the read mode. This condition can be checked by monitoring FLCS
[0] <RDY/BSY> (Table 23-13). If automatic programming has failed, the flash memory is
locked in the mode and will not return to the read mode. For returning to the read mode, it is
necessary to execute hardware reset to reset the flash memory or the device. In this case,
while writing to the address has failed, it is recommended not to use the device or not to use
the block that includes the failed address.
This condition can be checked by monitoring FLCS [0] <RDY/BSY> (See Table 23-13).
While no automatic verify operation is performed internally to the device, be sure to read the
data to confirm that data has been correctly erased. Any new command sequence is not
accepted while it is in an automatic chip erase operation. If it is desired to stop operation,
use the hardware reset function. If the operation is forced to stop, it is necessary to perform
the automatic chip erase operation again because the data erasing operation has not been
normally terminated.
Also, any protected blocks cannot be erased. If all the blocks are protected, the automatic
chip erase operation will not be performed and it returns to the read mode after completing
the sixth bus read cycle of the command sequence. When an automatic chip erase
operation is normally terminated, it automatically returns to the read mode. If an automatic
chip erase operation has failed, the flash memory is locked in the mode and will not return to
the read mode.
For returning to the read mode, it is necessary to execute hardware reset to reset the device.
In this case, the failed block cannot be detected. It is recommended not to use the device
anymore or to identify the failed block by using the block erase function for not to use the
identified block anymore.
This status of the automatic block erase operation can be checked by monitoring FLCS
<RDY/BSY> (See Table 23-13). While no automatic verify operation is performed internally
to the device, be sure to read the data to confirm that data has been correctly erased. Any
new command sequence is not accepted while it is in an automatic block erase operation. If
it is desired to stop operation, use the hardware reset function. In this case, it is necessary
to perform the automatic block erase operation again because the data erasing operation
Automatic block erase (fro aech block)
bus write cycle of the automatic page programming command.
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