TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 76

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

(1) Pushing during interrupt service routine
(2) Clearing interrupt factor
section describes what is recommended at the service routine programming and how the factor is
cleared.
register contents. The Cortex-M3 core automatically pushes the contents of PC, PSR, r0-r3, r12 and LR
to the stack. No extra programming is required for them.
service routine is being executed. Therefore, it is recommend to push the contents of the general purpose
register that might be rewritten.
CGICRCG register of the clock generator.
cleared. In this case, the factor needs to be cleared. Clearing the factor causes clearing the interrupt
request signal from clock generator.
setting the value which corresponds to the interrupt, to the CGICRCG register. The factor is detected
again when the specified edge appears again.
7.5.2.6 Interrupt Service Routine
Interrupt service routine requires specific programming according to the application to be used. This
Common interrupt service routine is accompanied with the interrupt handling and the pushing of the
Push the contents of other registers if needed.
An interrupt with the higher priority and faults such as NMI are accepted even when the interrupt
As for an interrupt factor clearing the standby mode, it need to clear the interrupt request with the
If “H” or “L” level signal is specified as the trigger to enter the active state, the factor is held unless it is
If a rising or falling edge is specified as the trigger to enter the active state, the factor is cleared by
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