TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 412

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

SP0CLK
SP0FSS
SP0DO
SP0DI
Hi-Z(Note1)
Note1)
Note2)
(c) Microwire frame format
Hi-Z(Note2)
Microwire frame format (single transfer)
Though the Microwire format is similar to the SPI format, it uses the master/slave message
transmission method for half-duplex communications. Each serial transmission is started by
an 8-bit control word, which is sent to the off-chip slave device. During this transmission, the
SSP does not receive input data. After the message has been transmitted, the off-chip slave
decodes it, and after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the requested data. The returned data can be 4 to 16 bits in length,
making the total frame length anywhere from 13 to 25 bits. With this configuration, during the
idle period:
• The SP0CLK signal is forcedly set to LOW.
• SP0FSS is forcedly set to HIGH.
• The transmit data line SP0DO is set to LOW.
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of
SP0FSS causes the value stored in the bottom entry of the transmit FIFO to be transferred to
the serial shift register for the transmit logic, and the MSB of the 8-bit control frame to be
shifted out onto the SP0DO pin. SP0FSS remains LOW and the SP0D1 pin remains tristated
during this transmission. The off-chip serial slave device latches each control bit into its serial
shifter on the rising edge of each SP0CLK. After the last bit is latched by the slave device, the
control byte is decoded during a one clock wait-state, and the slave responds by transmitting
data back to the SSP. Each bit is driven onto SP0DI line on the falling edge of SP0CLK. The
SSP in turn latches each bit on the rising edge of SP0CLK. At the end of the frame, for single
transfers, the SP0FSS signal is pulled HIGH one clock period after the last bit has been
latched in the receive serial shifter, which causes the data to be transferred to the receive
MSB
When transmission is disable , SP0DO terminal doesn’t output and is high impedance status. This
terminal needs to add suitable pull-up/down resistance to valid the voltage level.
SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high
impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage level.
8bit
TMPM380/M382 - 11 / 28 -
LSB
MSB
Hi-Z(Note1)
4 to 16bit
LSB
TMPM380/M382
Hi-Z(Note2)