TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 560

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TMPM382FSFG

Manufacturer Part Number
TMPM382FSFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM382FSFG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
64K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
64
Package
QFP(14x14)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
1
I2c/sio (ch)
1
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
10
16-bit Timer / Counter
6
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
22.5.2 Linked list operation
To operate the scatter/gather function, a transfer source and destination data areas need to be
defined by creating a set of Linked Lists first.
Each setting is called LLI (LinkedList).
Each LLI controls the transfer of one block of data. Each LLI indicates normal DMA setting and
controls transfer of successive data. Each time each DMA transfer is complete, the next LLI
setting will be loaded to continue the DMA operation (Daisy Chain).
An example of the setting is shown below.
1. The first DMA transfer setting should be made directly in the DMA register.
2. The second and subsequent DMA transfer settings should be written in the addresses of the
3. To stop up to N'th DMA transfer, set "next LLI AddressX" to 0x00000000.
+0
+4
+8
+C
memory set in "next LLI AddressX."
Directly set in the
DMA setting register
SourceAddress1
Destination Address1
next LLI Address2
Control register value
Transfer source memory
TMPM380/M382 - 25 / 26 -
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LLI address2
SourceAddress2
Destination Address2
next LLI Address2
Control register value
Destination memory
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LLI addressN
SourceAddressN
Destination AddressN
0x00000000
Control register value
TMPM380/M382

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