TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 110

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

CGIMCGE
0x4004_0230
7.6.3.5 CG Interrupt Mode Control Register E
This resister set the clearing standby request active level of interrupt
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
(Note1)
(Note2)
Refer to EMSTxx bit to know the active condition which is used for clearing
standby.
Please specify the bit for the edge first and then specify the bit for the <INTxEN>.
Setting them simultaneously is prohibited.
“0” is read
“0” is read
“0” is read
“0” is read
15
23
31
R
R
R
7
R
0
0
0
0
clear request.
standby clear request.
Active state setting of INTRTC standby
Write “010”
Active state setting of INTRMCRX
Write “011”
Write any value.
Write any value.
EMCGR
EMCGR
MCRX2
TC2
14
22
30
6
0
0
0
0
TMPM380/M382 - 55 / 59 -
011: Rising edge
EMCGR
EMCGR
MCRX1
010: Falling edge
R/W
R/W
TC1
R/W
R/W
13
21
29
5
1
1
1
1
EMCGR
EMCGR
MCRX0
TC0
12
20
28
4
0
0
0
0
standby clear request
standby clear request
Active state of INTRTC
Active state of
INTRMCRX
“00” is read.
“00” is read.
00: －
01: －
10: Falling edge
11: －
00: －
01: Rising edge
10:－
11: －
EMSRT
EMSTR
MCRX1
TC1
11
19
27
3
0
0
0
0
INTRTC,
R
R
R
R
EMSTR
EMSTR
MCRX0
TC0
10
18
26
2
0
0
0
0
INTRMCRX.
“0” is read. Write “0”.
“0” is read. Write “0”.
Reads as
undefined.
Reads as
undefined.
Undefined
Undefined
TMPM380/M382
17
25
1
R
9
R
R
R
0
0
INTRTC
clear input
0: Disable
1: Enable
INTRMCRX
clear input
0: Disable
1: Enable
INTRTC
INTRMC
RXEN
EN
R/W
R/W
R/W
R/W
16
24
0
8
0
0
0
0