TMPM382FSFG Toshiba, TMPM382FSFG Datasheet - Page 394

• Manufacturer Part Number: TMPM382FSFG
• Manufacturer: Toshiba

Specifications of TMPM382FSFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 64K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 64
• Package: QFP(14x14)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 1
• I2c/sio (ch): 1
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 10
• 16-bit Timer / Counter: 6
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

TMPM380/M382
Transmit and receive (full-duplex)
The full-duplex mode is enabled by setting bit 6 <FDPX0> of the serial mode control
register 1 (SC0MOD1) to “1”.
SCLK output mode
In the SCLK output mode, if SC0MOD2 <WBUF> is set to “0” and both the transmit
and receive double buffers are disabled, SCLK is output when the CPU writes data to
the transmit buffer. Subsequently, 8 bits of data are shifted into receive shift register
and the INTRX0 receive interrupt is generated. Concurrently, 8 bits of data written to
the transmit buffer are output from the TXD0 pin, the INTTX0 transmit interrupt is
generated when transmission of all data bits has been completed. Then, the SCLK
output stops. In this, the next round of data transmission and reception starts when the
data is read from the receive buffer and the next transmit data is written to the transmit
buffer by the CPU. The order of reading the receive buffer and writing to the transmit
buffer can be freely determined. Data transmission is resumed only when both
conditions are satisfied.
If SC0MOD2 <WBUF> = “1” and double buffering is enabled for both transmission and
reception, SCLK is output when the CPU writes data to the transmit buffer.
Subsequently, 8 bits of data are shifted into receive shift register, moved to receive
buffer, and the INTRX0 interrupt is generated. While 8 bits of data is received, 8 bits of
transmit data is output from the TXD0 pin. When all data bits are sent out, the INTTX0
interrupt is generated and the next data is moved from the Transmit Buffer to Transmit
shift register. If Transmit Buffer has no data to be moved to Transmit shift register
(SC0MOD2 <TBEMP> = 1) or when receive buffer is full (SC0MOD2 <RBFULL> = 1),
the SCLK clock is stopped. When both conditions, receive data is read and transmit
data is written, are satisfied, the SCLK output is resumed and the next round of data
transmission is started.
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