MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 1125

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Freescale Semiconductor
0x30 4812
0x30 4814 –
0x30 49FE
0x30 4A00 –
0x30 4A7E
0x30 4A80 –
0x30 4AFE
0x30 4B00 –
0x30 4B7E
0x30 4B80 –
0x30 4BFE
0x30 4C00
0x30 4C02
0x30 4C04
0x30 4C06
0x30 4C08
0x30 4C0A
0x30 4C0C
0x30 4C0E
0x30 4C10
0x30 4C12
0x30 4C14 –
0x30 4DFE
0x30 4E00 –
0x30 4E7E
0x30 4E80 –
0x30 4EFE
Address
Table B-10. QADC64E A and B (Queued Analog-to-Digital Converter) (continued)
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
—
—
S
T
S
1
1
QADC64MCR_B QADC64 Module Configuration Register
QADC64TEST_
QADC64INT_B
PORTQA_B/
PORTQB_B
DDRQA_B/
DDRQB_B
QASR1_A
RJURR_A
QACR0_B
QACR1_B
QACR2_B
QASR0_B
QASR1_B
RJURR_B
LJURR_A
LJSRR_A
Symbol
CCW_A
CCW_B
MPC561/MPC563 Reference Manual, Rev. 1.2
—
—
B
QADC64 Status Register 1.
See
descriptions.
Reserved
Conversion Command Word Table.
See
descriptions.
Result Word Table
Right-Justified, Unsigned Result Register.
See
bit descriptions.
Result Word Table
Left-Justified, Signed Result Register.
See
bit descriptions.
Result Word Table
Left-Justified, Unsigned Result Register.
See
bit descriptions.
QADC64 Test Register
Interrupt Register
Port A and Port B Data
Port A Data and Port B Direction Register
QADC64 Control Register 0
QADC64 Control Register 1
QADC64 Control Register 2
QADC64 Status Register 0
QADC64 Status Register 1
Reserved
Conversion Command Word Table
Result Word Table.
Right-Justified, Unsigned Result Register.
Table 13-17
Table 13-18
Section 13.3.10
Section 13.3.10
Section 13.3.10
QADC_B
and
and
Register
and
and
and
Table 14-18
Table 14-19
Section 14.3.10
Section 14.3.10
Section 14.3.10
for bit
for bit
for
for
for
Size
16
16
—
16
16
16
16
16
16
16
16
16
16
16
16
16
—
16
16
Internal Memory Map
Reset
—
—
—
S
U
X
X
X
S
S
U
S
S
S
S
S
S
U
X
B-15