MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 657

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Queued Serial Multi-Channel Module
15.6.6
Slave Mode
Clearing the MSTR bit in SPCR0 selects slave mode operation. In slave mode, the QSPI is unable to
initiate serial transfers. Transfers are initiated by an external SPI bus master. Slave mode is typically used
on a multi-master SPI bus. Only one device can be bus master (operate in master mode) at any given time.
Before QSPI operation is initiated, QSMCM register PQSPAR must be written to assign necessary pins to
the QSPI. The pins necessary for slave mode operation are MISO, MOSI, SCK, and PCS0/SS. MISO is
used for serial data output in slave mode, and MOSI is used for serial data input. Either or both may be
necessary, depending on the particular application. SCK is the serial clock input in slave mode and must
be assigned to the QSPI for proper operation. Assertion of the active-low slave select signal SS initiates
slave mode operation.
Before slave mode operation is initiated, DDRQS must be written to direct data flow on the QSPI pins
used. Configure the MOSI, SCK and PCS0/SS pins as inputs. The MISO pin must be configured as an
output.
After pins are assigned and configured, write data to be transmitted into transmit RAM. Command RAM
is not used in slave mode, and does not need to be initialized. Set the queue pointers, as appropriate.
When SPE is set and MSTR is clear, a low state on the slave select PCS0/SS pin begins slave mode
operation at the address indicated by NEWQP. Data that is received is stored at the pointer address in
receive RAM. Data is simultaneously loaded into the data serializer from the pointer address in transmit
RAM and transmitted. Transfer is synchronized with the externally generated SCK. The CPHA and CPOL
bits determine upon which SCK edge to latch incoming data from the MISO pin and to drive outgoing data
from the MOSI pin.
Because the command RAM is not used in slave mode, the CONT, BITSE, DT, DSCK, and peripheral
chip-select bits have no effect. The PCS0/SS pin is used only as an input.
The SPBR, DT and DSCKL fields in SPCR0 and SPCR1 bits are not used in slave mode. The QSPI drives
neither the clock nor the chip-select pins and thus cannot control clock rate or transfer delay.
Because the BITSE option is not available in slave mode, the BITS field in SPCR0 specifies the number
of bits to be transferred for all transfers in the queue. When the number of bits designated by BITS[3:0]
has been transferred, the QSPI stores the working queue pointer value in CPTQP, increments the working
queue pointer, and loads new transmit data from transmit RAM into the data serializer. The working queue
pointer address is used the next time PCS0/SS is asserted, unless the RCPU writes to NEWQP first.
The QSPI shifts one bit for each pulse of SCK until the slave select input goes high. If SS goes high before
the number of bits specified by the BITS field is transferred, the QSPI resumes operation at the same
pointer address the next time SS is asserted. The maximum value that the BITS field can have is 16. If
more than 16 bits are transmitted before SS is negated, pointers are incremented and operation continues.
The QSPI transmits as many bits as it receives at each queue address, until the BITS value is reached or
SS is negated. SS does not need to go high between transfers as the QSPI transfers data until reaching the
end of the queue, whether SS remains low or is toggled between transfers.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
15-39