MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 31

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

24.2.2
24.2.3
24.2.4
24.3
24.4
24.5
24.6
24.6.1
24.6.1.1
24.6.1.2
24.6.1.3
24.6.1.4
24.6.1.5
24.6.1.6
24.6.1.7
24.6.1.8
24.6.1.9
24.6.2
24.6.3
24.6.4
24.6.5
24.6.5.1
24.6.5.2
24.7
24.7.1
24.7.1.1
24.7.2
24.7.3
24.7.4
24.7.5
24.7.5.1
24.7.5.2
24.7.5.3
24.7.5.3.1
24.7.5.3.2
24.7.5.4
24.7.6
24.7.7
24.7.7.1
24.7.7.2
Freescale Semiconductor
Paragraph
Number
Parametrics .................................................................................................................... 24-4
Messages ....................................................................................................................... 24-4
Terms and Definitions .................................................................................................. 24-6
Programming Model ..................................................................................................... 24-8
Signal Interface ........................................................................................................... 24-20
Security ..................................................................................................................... 24-4
Normal ...................................................................................................................... 24-4
Disabled .................................................................................................................... 24-4
Register Map ............................................................................................................. 24-8
Accessing Memory-Mapped Locations Via
Accessing READI Tool Mapped Registers Via the Auxiliary Port ........................ 24-19
Partial Register Updates .......................................................................................... 24-19
Programming Considerations ................................................................................. 24-20
Functional Description ............................................................................................ 24-21
Functional Block Diagram ...................................................................................... 24-22
Message Priority ..................................................................................................... 24-22
Signal Protocol ........................................................................................................ 24-23
Messages ................................................................................................................. 24-24
READI Reset Configuration ................................................................................... 24-34
READI Signals ....................................................................................................... 24-36
User-Mapped Register (OTR) .............................................................................. 24-8
Tool-Mapped Registers ........................................................................................ 24-9
Device ID Register (DID) ..................................................................................... 24-9
Development Control Register (DC) .................................................................. 24-10
Mode Control Register (MC) .............................................................................. 24-11
User Base Address Register (UBA) ................................................................... 24-12
Read/Write Access Register (RWA) .................................................................. 24-13
Upload/Download Information Register (UDI) .................................................. 24-15
Data Trace Attributes 1 and 2 Registers (DTA1 and DTA2) ............................. 24-17
the Auxiliary Port ............................................................................................... 24-18
Program Trace Guidelines .................................................................................. 24-20
Compressed Code Mode Guidelines .................................................................. 24-20
Signals Implemented .......................................................................................... 24-21
Message Formats ................................................................................................ 24-28
Rules of Messages .............................................................................................. 24-31
Branch Trace Message Examples ....................................................................... 24-32
Non-Temporal Ordering of Transmitted Messages ............................................ 24-33
Reset Configuration for Debug Mode ................................................................ 24-36
Reset Configuration for Non-Debug Mode ........................................................ 24-37
Example of Indirect Branch Message ............................................................. 24-32
Example of Direct Branch Message ............................................................... 24-33
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
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Number
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