MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 841

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

19.4.1
Freescale Semiconductor
SRESET
Bits
1:2
3:4
0
5
6
7
8
Field STOP
Addr
TPU Module Configuration Register (TPUMCR)
MSB
TCR1P
TCR2P
0
0
Name
STOP
T2CG
SUPV
EMU
STF
1
TCR1P
Low-power stop mode enable. If the STOP bit in TPUMCR is set, the TPU3 shuts down its
internal clocks, shutting down the internal microengine. TCR1 and TCR2 cease to increment and
retain the last value before the stop condition was entered. The TPU3 asserts the stop flag (STF)
in TPUMCR to indicate that it has stopped.
0 Enable TPU3 clocks
1 Disable TPU3 clocks
Timer Count Register 1 prescaler control. TCR1 is clocked from the output of a prescaler. The
prescaler divides its input by 1, 2, 4, or 8. This is a write-once field unless the PWOD bit in
TPUMCR3 is set.
00 Divide by 1
01 Divide by 2
10 Divide by 4
11 Divide by 8
Refer to
Timer Count Register 2 prescaler control. TCR2 is clocked from the output of a prescaler. The
prescaler divides this input by 1, 2, 4, or 8. This is a write-once field unless the PWOD bit in
TPUMCR3 is set.
00 Divide by 1
01 Divide by 2
10 Divide by 4
11 Divide by 8
Refer to
Emulation control. In emulation mode, the TPU3 executes microinstructions from DPTRAM
exclusively. Access to the DPTRAM via the IMB3 is blocked, and the DPTRAM is dedicated for
use by the TPU3. After reset, this bit can be written only once.
0 TPU3 and DPTRAM operate normally
1 TPU3 and DPTRAM operate in emulation mode
TCR2 clock/gate control
0 TCR2 pin used as clock source for TCR2
1 TCR2 pin used as gate of DIV8 clock for TCR2
Refer to
Stop flag.
0 TPU3 is operating normally
1 TPU3 is stopped (STOP bit has been set)
Supervisor data space
0 Assignable registers are accessible from user or supervisor privilege level
1 Assignable registers are accessible from supervisor privilege level only
00
Figure 19-5. TPUMCR — TPU Module Configuration Register
2
Section 19.3.8, “Prescaler Control for
Section 19.3.9, “Prescaler Control for
Section 19.3.9, “Prescaler Control for
3
TCR2P
MPC561/MPC563 Reference Manual, Rev. 1.2
00
Table 19-7. TPUMCR Bit Description
4
0x30 4000(TPU_A), 0x30 4400 (TPU_B)
EMU T2CG STF SUPV PSCK TPU3 T2CSL
5
0
0
6
0
7
Description
8
1
TCR1” for more information.
TCR2” for more information.
TCR2” for more information.
1
0
9
10
1
11
0
12
Time Processor Unit 3
13
0000
—
14
LSB
15
19-11