MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 862
MPC564MZP66
Manufacturer Part Number
MPC564MZP66
Description
IC MCU 512K FLASH 66MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP66
Core Processor
PowerPC
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Dual-Port TPU3 RAM (DPTRAM)
When the DPTRAM array is being used by one or two of the TPU3 units, all accesses via the IMB3 are
disabled. The control registers have no effect on the RAM array.
The contents of the RAM are validated using a multiple input signature calculator (MISC). MISC reads of
the RAM are performed only when the MPC561/MPC563 is in emulation mode and the MISC is enabled
(MISEN = 1 in the DPTMCR).
Refer to
Section 19.3.6, “Emulation
Support” for more information in TPU3 and DPTRAM operation in
emulation mode.
20.5
Multiple Input Signature Calculator (MISC)
The integrity of the DPTRAM data is ensured through the use of a MISC. The DPTRAM data is read in
reverse address order and a unique 32-bit signature is generated based on the output of these reads. MISC
reads are performed when one of the TPU3 modules does not request back-to-back accesses to the
DPTRAM provided that the MISEN bit in the DPTMCR is set.
The MISC generates the DPTRAM signature based on the following polynomial:
31
2
22
G x ( )
=
1
+ +
x
x
+
x
+
x
Eqn. 20-1
After the entire DPTRAM has been read and a signature has been calculated, the MISC sets the MISF bit
in the DPTMCR. The host should poll this bit and enter a handling routine when the bit is found to be set.
The signature should then be read from the MISRH and MISRL registers and the host determines if it
matches the predetermined signature.
The MISRH and MISRL registers are updated each time the MISC completes reading the entire DPTRAM
regardless of whether or not the previous signature has been read or not. This ensures that the host reads
the most recently generated signature.
The MISC can be disabled by clearing the MISEN bit in the DPTMCR.
NOTE
The reset state of the DPTMCR[MISEN] is disabled.
MPC561/MPC563 Reference Manual, Rev. 1.2
20-8
Freescale Semiconductor
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