MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 191

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

When a machine-check exception occurs, the processor does one of the following:
Which action is taken depends on the value of the MSR[ME] bit, whether or not debug mode was enabled
at reset, and (if debug mode is enabled) the values of the CHSTPE (checkstop enable) and MCIE (machine
check enable) bits in the debug enable register (DER).
processor is in the checkstop state, instruction processing is suspended and cannot be restarted without
resetting the core.
An indication is sent to the USIU which may generate an automatic reset in this condition. Refer to
Chapter 7,
The register settings for machine check exceptions are shown in
Freescale Semiconductor
•
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Takes a machine check exception;
Enters the checkstop state; or
Enters debug mode.
MSR[ME]
“Reset,” for more details.
Register Name
0
1
0
0
1
1
Debug Mode
Table 3-25. Register Settings following a Machine Check Exception
Enable
Table 3-24. Machine Check Exception Processor Actions
0
0
1
1
1
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
CHSTPE
16:31
10:15
X
X
X
X
0
1
5:9
Bits
2:4
All
0
1
2
2
2
Set to the effective address of the instruction that caused the
interrupt
MSR0
Set to 1 for instruction fetch-related errors and 0 for
load/store-related errors
Cleared to 0
MSR[5:9]
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
MCIE
X
X
X
X
0
1
Table 3-24
Action Performed when Exception Detected
Branch to machine-check exception handler
Branch to machine-check exception handler
Table
summarizes the possibilities. When the
Enter checkstop state
Enter checkstop state
Description
Enter debug mode
Enter debug mode
3-25.
Central Processing Unit
3-47