MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 185

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.13.8
3.13.8.1
The core implements the following instructions:
All instructions are defined for the fixed-point processor in the UISA in the hardware. For performance of
the various instructions, refer to
3.13.9
3.13.9.1
The RCPU implements all floating-point features as defined in the UISA, including the non-IEEE working
mode. Some features require software assistance. For more information refer to the RCPU Reference
Manual (Floating-point Load Instructions).
3.13.9.2
The only optional instruction implemented by RCPU hardware is store floating-point as integer word
indexed (stfiwx). An attempt to execute any other optional instruction causes an implementation
dependent software emulation exception.
Freescale Semiconductor
•
•
•
•
•
•
Fixed-point arithmetic instructions
Fixed-point compare instructions
Fixed-point trap instructions
Fixed-point logical instructions
Fixed-point rotate and shift instructions
Move to/from system register instructions
— Move To/From System Register Instructions. Move to/from invalid special registers in which
— Fixed-Point Arithmetic Instructions. If an attempt is made to perform any of the divisions in
SPR0 = 1 yields invocation of the privilege instruction error interrupt handler if the processor
is in problem state. For a list of all implemented special registers, refer to
Table
the divw[o][.] instruction (0x80000000
0x80000000; if Rc =1, the contents of bits in CR field 0 are LT = 1, GT = 0, EQ = 0, and SO is
set to the correct value. If an attempt is made to perform any of the divisions in the divw[o][.]
instruction, <anything>
for 64-bit implementations. In 32-bit implementations, if L = 1 the instruction form is invalid.
The core ignores this bit and therefore, the behavior when L = 1 is identical to the valid form
instruction with L = 0
Fixed-Point Processor
Floating-Point Processor
Fixed-Point Instructions
General
Optional Instructions
3-3.
Table
MPC561/MPC563 Reference Manual, Rev. 1.2
÷
0. In cmpi, cmp, cmpli, and cmpl instructions, the L-bit is applicable
3-20.
÷
-1, <anything>
÷
0), then the contents of rD are
Table
Central Processing Unit
3-2, and
3-41