MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 457

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 12-2
cycle. It is assumed that the IMB3 is available to the UIMB at all times (fastest possible case).
12.4
The interrupts from the modules on the IMB3 are propagated to the interrupt controller in the USIU
through the UIMB interface. The UIMB interrupt synchronizer latches the interrupts from the modules on
the IMB3 and drives them onto the U-bus, where they are latched by the USIU interrupt controller.
12.4.1
The IMB3 has eight interrupt lines. There can be a maximum of 32 levels of interrupts from the modules
on IMB3 bus. A single module can be a source for more than one interrupt. For example, the QSMCM can
generate two interrupts (one for QSCI1/QSCI2 and another for QSPI). In this case, the QSMCM has two
interrupt sources. Each of these two sources can assert the interrupt on any of the 32 levels.
Freescale Semiconductor
Interrupt Operation
shows the number of system clock cycles that the UIMB requires to perform each type of bus
Interrupt Sources and Levels on IMB3
IMB3 Clock
The UIMB interface dynamically interprets the port size of the addressed
module during each bus cycle, allowing bus transfers to and from 16-bit and
32-bit IMB3 modules. During a bus transaction, the slave module on the
IMB3 signals its port size (16- or 32-bit) via an internal port size signal.
IMB3 Clock
CLKOUT
CLKOUT
Bus Cycle (from U-bus Transfer Start
to U-bus Transfer Acknowledge)
Dynamically-sized write
Dynamically-sized read
Table 12-2. Bus Cycles and System Clock Cycles
Figure 12-3. IMB3 Clock – Half-Speed IMB3 Bus
Normal write
Figure 12-2. IMB3 Clock – Full-Speed IMB3 Bus
Normal read
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
Number of System Clock Cycles
Full Speed
6
4
4
6
Half Speed
U-Bus to IMB3 Bus Interface (UIMB)
10
10
6
6
12-3