MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 395
MPC564MZP66
Manufacturer Part Number
MPC564MZP66
Description
IC MCU 512K FLASH 66MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP66
Core Processor
PowerPC
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Note: the delay for the internal to external cycle may be one clock or greater.
9.5.14
Show cycles are representations of RCPU accesses to internal devices of the MPC561/MPC563. These
accesses are driven externally for emulation, visibility, and debugging purposes. A show cycle can have
one address phase and one data phase, or just an address phase in the case of instruction show cycles. The
cycle can be a write or a read access. The data for both the read and write accesses should be driven by the
bus master. (This is different from normal bus read and write accesses.) The address and data of the show
cycle must each be valid on the bus for one clock. The data phase must not require a transfer acknowledge
to terminate the bus show cycle.
Freescale Semiconductor
CLKOUT
BR
BG (output)
BB
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (output)
Show Cycle Transactions
Figure 9-40. Retry of External Master Access (Internal Arbiter)
ADDR (external)
MPC561/MPC563 Reference Manual, Rev. 1.2
O
Allow Internal
Access to Gain the
Bus
ADDR (internal)
External Bus Interface
9-55
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