MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 423
MPC564MZP66
Manufacturer Part Number
MPC564MZP66
Description
IC MCU 512K FLASH 66MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP66
Core Processor
PowerPC
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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With dual mapping, aliasing of address spaces may occur. This happens when the region is dual-mapped
into a region which is also mapped into one of the four regions available in the memory controller. If code
or data is written to the dual-mapped region, care must be taken to avoid overwriting this code or data by
normal accesses of the chip-select region.
There is a match if:
Care must also be taken to avoid overwriting “normal” CSx data with dual-mapped code or data.
One way to avoid this situation is by disabling the chip-select region and enabling only the dual-mapped
region (DMBR[DME] = 1, but BRx[V] = 0).
Freescale Semiconductor
•
•
The attributes for the access are taken from one of the base and option registers of the appropriate
chip select
The chip-select region selected is determined by the CS line select bit field
“Dual-Mapping Base Register
where BA represents the bit field in the DMBR register.
bus_address[0:16] == {0000000,ISB[0:2],0,BA[1:6]}
MPC561/MPC563 Reference Manual, Rev. 1.2
(DMBR)”).
Figure 10-19
illustrates the phenomenon.
(Section 10.9.5,
Memory Controller
Eqn. 10-1
Eqn. 10-2
10-25
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