MPC564MZP66 Freescale Semiconductor, MPC564MZP66 Datasheet - Page 502

• Manufacturer Part Number: MPC564MZP66
• Description: IC MCU 512K FLASH 66MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP66

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

QADC64E Legacy Mode Operation
13.5.1
Queue 1 has priority over queue 2 execution. The following cases show the conditions under which queue
1 asserts its priority:
13.5.2
The pause feature can be used to divide queue 1 and/or queue 2 into multiple sub-queues. A sub-queue is
defined by setting the pause bit in the last CCW of the sub-queue.
Figure 13-23
shown with four CCWs in each sub-queue and queue 2 has two CCWs in each sub-queue.
13-38
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When a queue is not active, a trigger event for queue 1 or queue 2 causes the corresponding queue
execution to begin.
When queue 1 is active and a trigger event occurs for queue 2, queue 2 cannot begin execution until
queue 1 reaches completion or the paused state. The status register records the trigger event by
reporting the queue 2 status as trigger pending. Additional trigger events for queue 2, which occur
before execution can begin, are captured as trigger overruns.
When queue 2 is active and a trigger event occurs for queue 1, the current queue 2 conversion is
aborted. The status register reports the queue 2 status as suspended. Any trigger events occurring
for queue 2 while queue 2 is suspended are captured as trigger overruns. Once queue 1 reaches the
completion or the paused state, queue 2 begins executing again. The programming of the RESUME
bit in QACR2 determines which CCW is executed in queue 2. Refer to
Register 2
When simultaneous trigger events occur for queue 1 and queue 2, queue 1 begins execution and
the queue 2 status is changed to trigger pending.
Queue Priority
Paused Sub-Queues
shows the CCW format and an example of using pause to create sub-queues. Queue 1 is
(QACR2)” for more information.
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 13.3.7, “Control
Freescale Semiconductor