MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1000

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory Map/Register Definition
1000
TWRNMSK
RWRNMSK
BOFFMSK
ERRMSK
CLKSRC
Field
LPB
15
14
13
12
11
10
Phase Buffer Segment 2 = (PSEG2 + 1) x Time-Quanta.
Bus Off Mask
This bit provides a mask for the Bus Off Interrupt.
0
1
Error Mask
This bit provides a mask for the Error Interrupt.
0
1
CAN Engine Clock Source
This bit selects the clock source to the CAN Protocol Engine (PE) to be either the peripheral clock (driven
by the PLL) or the crystal oscillator clock. The selected clock is the one fed to the prescaler to generate
the Serial Clock (Sclock). In order to guarantee reliable operation, this bit can only be written in Disable
mode as it is blocked by hardware in other modes. See Section "Protocol Timing".
0
1
Loop Back Mode
This bit configures FlexCAN to operate in Loop-Back Mode. In this mode, FlexCAN performs an internal
loop back that can be used for self test operation. The bit stream output of the transmitter is fed back
internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
recessive state (logic ‘1’). FlexCAN behaves as it normally does when transmitting, and treats its own
transmitted message as a message received from a remote node. In this mode, FlexCAN ignores the bit
sent during the ACK slot in the CAN frame acknowledge field, generating an internal acknowledge bit to
ensure proper reception of its own message. Both transmit and receive interrupts are generated. This bit
can only be written in Freeze mode as it is blocked by hardware in other modes.
NOTE: In this mode, the MCR[SRXDIS] cannot be asserted because this will impede the self reception
0
1
Tx Warning Interrupt Mask
This bit provides a mask for the Tx Warning Interrupt associated with the TWRNINT flag in the Error and
Status Register. This bit is read as zero when MCR[WRNEN] bit is negated. This bit can only be written if
MCR[WRNEN] bit is asserted.
0
1
Rx Warning Interrupt Mask
This bit provides a mask for the Rx Warning Interrupt associated with the RWRNINT flag in the Error and
Status Register. This bit is read as zero when MCR[WRNEN] bit is negated. This bit can only be written if
MCR[WRNEN] bit is asserted.
Bus Off interrupt disabled
Bus Off interrupt enabled
Error interrupt disabled
Error interrupt enabled
The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock
frequency must be lower than the bus clock.
The CAN engine clock source is the peripheral clock.
Loop Back disabled
Loop Back enabled
Tx Warning Interrupt disabled
Tx Warning Interrupt enabled
of a transmitted message.
CANx_CTRL1 field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Description
Freescale Semiconductor, Inc.