MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 63

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

3.2.1.2 System Tick Timer
The System Tick Timer's clock source is always the core clock, FCLK. This results in the
following:
3.2.1.3 Debug facilities
This device has extensive debug capabilities including run control and tracing
capabilities. The standard ARM debug port that supports JTAG and SWD interfaces.
Also the cJTAG interface is supported on this device.
3.2.1.4 Core privilege levels
The ARM documentation uses different terms than this document to distinguish between
privilege levels.
Freescale Semiconductor, Inc.
Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is
Data code (DCODE) bus
System bus
Private peripheral (PPB) bus
Privileged
Unprivileged or user
If you see this term...
• The CLKSOURCE bit in SysTick Control and Status register is always set to select
• Because the timing reference (FCLK) is a variable frequency, the TENMS bit in the
• The NOREF bit in SysTick Calibration Value Register is always set, implying that
the core clock.
SysTick Calibration Value Register is always zero.
FCLK is the only available source of reference timing.
Bus name
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
connected to the crossbar switch via a single master port. In addition, the CODE bus is also
tightly coupled to the lower half of the system RAM (SRAM_L).
The system bus is connected to a separate master port on the crossbar. In addition, the
system bus is tightly coupled to the upper half system RAM (SRAM_U).
The PPB provides access to these modules:
• ARM modules such as the NVIC, ETM, ITM, DWT, FBP, and ROM table
• Freescale Miscellaneous Control Module (MCM)
Supervisor
User
it also means this term...
Description
Chapter 3 Chip Configuration
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