MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 540

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Initialization / Application Information
24.5.3.2 Example 2: Moving from PEE to BLPI Mode: MCGOUTCLK
In this example, the MCG will move through the proper operational modes from PEE
mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see
previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency.First, the code
sequence will be described. Then a flowchart will be included which illustrates the
sequence.
540
1. First, PEE must transition to PBE mode:
2. Then, PBE must transition either directly to FBE mode or first through BLPE mode
3. Next, FBE mode transitions into FBI mode:
and then to FBE mode:
b. Loop until S[CLKST] are 2'b10, indicating that the external reference clock is
b. BLPE/FBE: C6 = 0x00
d. FBE: Loop until S[PLLST] is cleared, indicating that the current source for the
a. C1 = 0x90
a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1
c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to
a. C1 = 0x54
selected to feed MCGOUTCLK.
FBE mode.
PLLS clock is the FLL.
• C1[CLKS] set to 2'b10 in order to switch the system clock source to the
• C6[PLLS] clear to 0 to select the FLL. At this time, with C1[FRDIV] value
Frequency =32 kHz
external reference clock.
of 3'b010, the FLL divider is set to 128, resulting in a reference frequency of
4 MHz / 128 = 31.25 kHz. If C1[FRDIV] was not previously set to 3'b010
(necessary to achieve required 31.25-39.06 kHz FLL reference frequency
with an 4 MHz external source frequency), it must be changed prior to
clearing C6[PLLS] bit. In BLPE mode,changing this bit only prepares the
MCG for FLL usage in FBE mode. With C6[PLLS] = 0, the C6[VDIV]
value does not matter.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.